Masaya Yoshikawa

According to our database, Masaya Yoshikawa authored at least 95 papers between 2002 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2023

Tamper Resistance Evaluation of Midori128 against Differential Power Analysis.

Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa

Proceedings of the 6th IEEE International Conference on Knowledge Innovation and Invention, 2023

Implementation and Evaluation of the Lightweight Cipher SPARKLE.

Masato Sato, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 6th International Conference on Electronics, 2023

Explainable AI based Adversarial Examples and its Evaluation.

Ryo Kumagai, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 6th International Conference on Electronics, 2023

Machine Learning Based Power Analysis for Simon with Secure Mechanism.

Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 15th International Conference on Computer and Automation Engineering, 2023

Deep Learning Based Side-Channel Analysis for Lightweight Cipher PRESENT.

Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa

Proceedings of the 15th International Conference on Computer and Automation Engineering, 2023

Security Evaluation of Glitch Based Authentication Function for Edge AI.

Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa

Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

Hamming Weight aware Fault Analysis for Lightweight Cryptography TWINE.

Yusuke Nozaki, Shu Takemoto, Masaya Yoshikawa

Proceedings of the 8th International Conference on Cloud Computing and Internet of Things, 2023

2022

AI Hardware Oriented Trojan Detection Architecture.

Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the ICECC 2022: The 5th International Conference on Electronics, Communications and Control Engineering, Higashi-ku, Japan, March 25, 2022

Authenticated Encryption based Secure In-vehicle System against DoS Attacks.

Daichi Hirose, Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022

2021

Neural Network Based Glitch Physically Unclonable Function.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 12th IEEE Annual Ubiquitous Computing, 2021

Performance Evaluation of Unrolled Cipher based Glitch PUF Implemented on Virtex-7.

Yusuke Nozaki, Shu Takemoto, Yoshiya Ikezaki, Masaya Yoshikawa

Proceedings of the 4th International Symposium on Devices, Circuits and Systems, 2021

Hardware Trojan for Lightweight Cryptoraphy Elephant.

Shu Takemoto, Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 10th IEEE Global Conference on Consumer Electronics, 2021

2020

Tamper Resistance Evaluation of TWINE Implemented on 8-bit Microcontroller.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the ICSIM '20: The 3rd International Conference on Software Engineering and Information Management, 2020

Unrolled PRINCE Cipher based Glitch Physically Unclonable Function.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the ICISS 2020: The 3rd International Conference on Information Science and System, 2020

2019

Security Evaluation of Ring Oscillator PUF Against Genetic Algorithm Based Modeling Attack.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the Innovative Mobile and Internet Services in Ubiquitous Computing, 2019

Side-Channel Resistance Evaluation Method using Statistical Tests for Physical Unclonable Function.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the International Conference on Artificial Intelligence in Information and Communication, 2019

Scalability and Performance Evaluation of GA Based Modeling Analysis for RO PUF.

Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Evaluation of the Hiding-Countermeasure PRINCE Using Differential Power Analysis.

Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Quantitative Performance Evaluation of PL PUF and RO PUF with ASIC Implementation.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Security Evaluation of Counter Synchronization Method for CAN Against DoS Attack.

Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019

Side-Channel Analysis for Searchable Encryption System and its Security Evaluation.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the 2019 IEEE International Conference on Computational Science and Engineering, 2019

Secret Sharing Schemes Based Secure Authentication for Physical Unclonable Function.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 4th International Conference on Computer and Communication Systems, 2019

Countermeasure of Lightweight Physical Unclonable Function Against Side-Channel Attack.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the Cybersecurity and Cyberforensics Conference, 2019

Performance Evaluation of CAESAR Authenticated Encryption on SROS2.

Shu Takemoto, Kanata Nishida, Yusuke Nozaki, Masaya Yoshikawa, Shinya Honda, Ryo Kurachi

Proceedings of the AICCC 2019: 2nd Artificial Intelligence and Cloud Computing Conference, 2019

Statistical Power Analysis for IoT Device Oriented Encryption with Glitch Canceller.

Shu Takemoto, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 11th IEEE International Workshop on Computational Intelligence and Applications, 2019

2018

Implementation of Searchable Encryption System with Dedicated Hardware and its Evaluation.

Masaya Yoshikawa, Yoshiya Ikezaki, Yusuke Nozaki

Proceedings of the 9th IEEE Annual Ubiquitous Computing, 2018

Lightweight Cipher Aware Countermeasure Using Random Number Masks and Its Evaluation.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the 2nd International Conference on Vision, Image and Signal Processing, 2018

EM based machine learning attack for XOR arbiter PUF.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 2nd International Conference on Machine Learning and Soft Computing, 2018

Lethal Genes Aware Genetic Programming Analysis for RO PUF.

Taichi Umeda, Kazuya Shibagaki, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

Feasibility Evaluation of Neural Network Physical Unclonable Function.

Kazuya Shibagaki, Taichi Umeda, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

Shuffling Based Side-Channel Countermeasure for Energy Harvester.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 7th Global Conference on Consumer Electronics, 2018

Security Evaluation of a Lightweight Cipher SPECK against Round Addition DFA.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 2018 Artificial Intelligence and Cloud Computing Conference, 2018

Feature Extraction Driven Modeling Attack Against Double Arbiter PUF and Its Evaluation.

Susumu Matsumi, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 2018 Artificial Intelligence and Cloud Computing Conference, 2018

2017

Electromagnetic analysis method for ultra low power cipher Midori.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the 8th IEEE Annual Ubiquitous Computing, 2017

Helper Data Aware Cloning Method for Physical Unclonable Function.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the 2017 IEEE International Conference on Smart Cloud, 2017

Statistical fault analysis for a lightweight cipher midori.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE International Conference on Information and Automation, 2017

Tamper resistance evaluation of PUF implementation against machine learning attack.

Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the 2017 International Conference on Biometrics Engineering and Application, 2017

Power analysis for a lightweight authenticated encryption SIMON-JAMBU.

Yusuke Nozaki, Yoshiya Ikezaki, Hideki Nagata, Masaya Yoshikawa

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

FPGA implementation technique for power consumption aware tamper resistance accelerator of lightweight PUF.

Yoshiya Ikezaki, Yusuke Nozaki, Hideki Nagata, Masaya Yoshikawa

Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017

Hierarchical power analysis attack for falsification detection cipher.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the IEEE 7th Annual Computing and Communication Workshop and Conference, 2017

2016

Two Stage Fault Analysis against a Falsification Detection Cipher Minalpher.

Masaya Yoshikawa, Yusuke Nozaki

Proceedings of the 2016 IEEE International Conference on Smart Cloud, 2016

Hardware Trojan for an authenticated encryption Minalpher.

Yusuke Nozaki, Yoshiya Ikezaki, Masaya Yoshikawa

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

Deep learning attack for physical unclonable function.

Yoshiya Ikezaki, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 5th Global Conference on Consumer Electronics, 2016

Multiple Rounds Aware Power Analysis Attack for a Lightweight Cipher SIMECK.

Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi

Proceedings of the Second IEEE International Conference on Big Data Computing Service and Applications, 2016

Vulnerability Evaluation Accelerator for Lightweight Ciphers.

Masaya Yoshikawa, Yusuke Nozaki, Kensaku Asahi

Proceedings of the 2nd IEEE International Conference on Big Data Security on Cloud, 2016

2015

Secure in-vehicle Systems using Authentication.

Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi

Int. J. Networked Distributed Comput., 2015

Frequency Domain Aware Power Analysis Attack against Random Clock LSI for Secure Automotive Embedded Systems.

Masaya Yoshikawa, Yusuke Nozaki, Toshiya Asai, Kensaku Asahi

Proceedings of the IEEE 82nd Vehicular Technology Conference, 2015

Power analysis for clock fluctuation LSI.

Yusuke Nozaki, Toshiya Asai, Kensaku Asahi, Masaya Yoshikawa

Proceedings of the 16th IEEE/ACIS International Conference on Software Engineering, 2015

Design and LSI prototyping of security module with hardware trojan.

Masaya Yoshikawa, Takuya Tsukadaira, Takeshi Kumaki

Proceedings of the IEEE International Conference on Consumer Electronics, 2015

Statistical fault analysis for a lightweight block cipher TWINE.

Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Hardware Trojan for ultra lightweight block cipher Piccolo.

Kohei Nohara, Yusuke Nozaki, Masaya Yoshikawa

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Detection technique for hardware Trojans using machine learning in frequency domain.

Takato Iwase, Yusuke Nozaki, Masaya Yoshikawa, Takeshi Kumaki

Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

Secure in-vehicle systems against Trojan attacks.

Masaya Yoshikawa, Kyota Sugioka, Yusuke Nozaki, Kensaku Asahi

Proceedings of the 14th IEEE/ACIS International Conference on Computer and Information Science, 2015

2014

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks.

Mitsuru Shiozaki, Kousuke Ogawa, Kota Furuhashi, Takahiko Murayama, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Error value driven fault analysis attack.

Masaya Yoshikawa, Hikaru Goto, Kensaku Asahi

Proceedings of the 15th IEEE/ACIS International Conference on Software Engineering, 2014

Vulnerability evaluation of multiplexing PUF for SVM attacks.

S. Kiryu, Kensaku Asahi, Masaya Yoshikawa

Proceedings of the Progress in Systems Engineering, 2014

PUF ID generation method for modeling attacks.

Yusuke Nozaki, Kensaku Asahi, Masaya Yoshikawa

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

Study of threat for automotive embedded system by Trojan virus.

Kohei Nohara, Kensaku Asahi, Masaya Yoshikawa

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2013

The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3.

Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino

Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Cipher-destroying and secret-key-emitting hardware Trojan against AES core.

Takeshi Kumaki, Masaya Yoshikawa, Takeshi Fujino

Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Platform for Verification of Electromagnetic Analysis Attacks against Cryptographic Circuits.

Masaya Yoshikawa, Toshiya Asai

Proceedings of the Tenth International Conference on Information Technology: New Generations, 2013

Hardware Trojan for security LSI.

Masaya Yoshikawa, R. Satoh, Takeshi Kumaki

Proceedings of the IEEE International Conference on Consumer Electronics, 2013

2012

High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.

Mitsuru Shiozaki, Kota Furuhashi, Takahiko Murayama, Akitaka Fukushima, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Electron., 2012

Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System.

Ryohei Hori, Taisuke Ueoka, Taku Otani, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation.

Ryohei Hori, Tatsuya Kitamori, Taisuke Ueoka, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Multiplexing aware arbiter physical unclonable function.

Masaya Yoshikawa, Akira Naruse

Proceedings of the IEEE 13th International Conference on Information Reuse & Integration, 2012

2011

Placement Tool Dedicated for a Via-Programmable Logic Device VPEX.

Masaya Yoshikawa, Takeshi Fujino

Int. J. Comput. Their Appl., 2011

Multi-rounds masking method against DPA attacks.

Masaya Yoshikawa, M. Sugiyama

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2011

Efficient Random Number for the Masking Method against DPA Attacks.

Masaya Yoshikawa, Y. Kojima

Proceedings of the 21st International Conference on Systems Engineering (ICSEng 2011), 2011

A power grid optimization algorithm considering via reliability.

Masahiro Fukui, Haruo Miki, Masaya Yoshikawa, Shuji Tsukiyama

Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010

Hybrid Ant Colony Optimization for intensification and diversification.

Masaya Yoshikawa, Shimohigashi Yoshiaki

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2010

Placement Tool Dedicated for a Via-programmable Logic Device VPEX.

Masaya Yoshikawa, Yuichi Kokusyo, Takeshi Fujino

Proceedings of the ISCA 23rd International Conference on Computer Applications in Industry and Engineering, 2010

2009

Dedicated Hardware for Ant Colony Optimization Using Distributed Memory.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

An Efficient Hardware Accelerator for Power Grid Simulation.

Taiki Hashizume, Hisako Sugano, Shinichi Nishizawa, Masaya Yoshikawa, Masahiro Fukui

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Adaptive Immune Algorithm Considering Intensification and Diversification.

Masaya Yoshikawa, Akira Naruse, Shinsuke Souboku

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2009

OX Hardware Engine for High Speed Character Inheritance.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2009 International Conference on Genetic and Evolutionary Methods, 2009

Car Navigation System Based on Hybrid Genetic Algorithm.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the CSIE 2009, 2009 WRI World Congress on Computer Science and Information Engineering, March 31, 2009

2008

Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing.

Akihiro Nakamura, Masahide Kawarasaki, Kouta Ishibashi, Masaya Yoshikawa, Takeshi Fujino

IEICE Trans. Electron., 2008

Hybrid Architecture of Genetic Algorithm and Simulated Annealing.

Masaya Yoshikawa, Hironori Yamauchi, Hidekazu Terai

Eng. Lett., 2008

Route selection algorithm based on integer operation Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2008

Hardware Architecture of Pheromone-Balance Aware Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2008 International Conference on Genetic and Evolutionary Methods, 2008

2007

Hierarchical Parallel Placement Using a Genetic Algorithm for Realizing Low Power Consumption.

Masaya Yoshikawa, Hidekazu Terai

J. Adv. Comput. Intell. Intell. Informatics, 2007

The new DFM approach based on a genetic algorithm.

Masaya Yoshikawa, Hidekazu Terai

Artif. Life Robotics, 2007

Architecture for high-speed Ant Colony Optimization.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE International Conference on Information Reuse and Integration, 2007

Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing.

Akihiro Nakamura, Masahide Kawaharazaki, Masaya Yoshikawa, Takeshi Fujino

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Dedicated Floorplanning Engine Architecture Based on Genetic Algorithm and Evaluation.

Masaya Yoshikawa, Hidekazu Terai

J. Adv. Comput. Intell. Intell. Informatics, 2006

Apriori, Association Rules, Data Mining, Frequent Itemsets Mining (FIM), Parallel Computing.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Fourth International Conference on Software Engineering, 2006

Immune Algorithm Processor.

Masaya Yoshikawa, Masahiro Fukui, Hidekazu Terai

Proceedings of the 21st International Conference on Computers and Their Applications, 2006

Co-evolutionary robotics using two kinds of neural networks.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the ISCA 19th International Conference on Computer Applications in Industry and Engineering, 2006

2005

Asynchronous Parallel Genetic Algorithm for Congestion-Driven Placement Technique.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Third ACIS International Conference on Software Engineering, 2005

A Hierarchical Parallel Placement Technique based on Genetic Algorithm.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the Fifth International Conference on Intelligent Systems Design and Applications (ISDA 2005), 2005

Hybrid genetic algorithm engine for high-speed floorplanning.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Performance driven placement technique based on collaboration of software and hardware.

Masaya Yoshikawa, Hidekazu Terai

Proceedings of the IEEE Congress on Evolutionary Computation, 2005

2004

VLSI processor architecture for real-time GA processing and PE-VLSI design.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2002

Scalable GA processor architecture and its implementation of processor-element.

Tetsuya Imai, Masaya Yoshikawa, Hidekazu Terai, Hironori Yamauchi

Proceedings of the IEEE International Conference on Acoustics, 2002