Takeshi Fujino

Orcid: 0000-0001-9441-3137

According to our database1, Takeshi Fujino authored at least 71 papers between 1997 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
SEDMA: Self-Distillation with Model Aggregation for Membership Privacy.
Proc. Priv. Enhancing Technol., January, 2024

Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2023
Practical aspects on non-profiled deep-learning side-channel attacks against AES software implementation with two types of masking countermeasures including RSM.
J. Cryptogr. Eng., November, 2023

Exploring Effect of Residual Electric Charges on Cryptographic Circuits: Extended Version.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

Profiling Deep Learning Side-Channel Attacks Using Multi-Label against AES Circuits with RSM Countermeasure.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., March, 2023

Backdoor Attack on Deep Neural Networks Triggered by Fault Injection Attack on Image Sensor Interface.
Sensors, 2023

Evaluation of Model Quantization Method on Vitis-AI for Mitigating Adversarial Examples.
IEEE Access, 2023

Multispectral Pedestrian Detection with Visible and Far-infrared Images Under Drifting Ambient Light and Temperature.
Proceedings of the 2023 IEEE SENSORS, Vienna, Austria, October 29 - Nov. 1, 2023, 2023

Evaluation of Membership Inference Attack Against Federated Learning With Differential Privacy on Edge Devices.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023

2022
Adversarial Scan Attack against Scan Matching Algorithm for Pose Estimation in LiDAR-Based SLAM.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Experimental Study of Fault Injection Attack on Image Sensor Interface for Triggering Backdoored DNN Models.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Fault Injection Attacks Utilizing Waveform Pattern Matching against Neural Networks Processing on Microcontroller.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2022

Deep Learning-Based Side-Channel Attacks against Software-Implemented RSA using Binary Exponentiation with Dummy Multiplication.
Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), 2022

Deep Learning Side-Channel Attacks against Hardware-Implemented Lightweight Cipher Midori 64.
Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), 2022

Fundamental Study of Adversarial Examples Created by Fault Injection Attack on Image Sensor Interface.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2022

Towards Isolated AI Accelerators with OP-TEE on SoC-FPGAs.
Proceedings of the Applied Cryptography and Network Security Workshops, 2022

2021
Deep learning side-channel attack against hardware implementations of AES.
Microprocess. Microsystems, November, 2021

Timing Black-Box Attacks: Crafting Adversarial Examples through Timing Leaks against DNNs on Embedded Devices.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Area-Efficient Post-Processing Circuits for Physically Unclonable Function with 2-Mpixel CMOS Image Sensor.
Sensors, 2021

Simple electromagnetic analysis attack based on geometric leak on ASIC implementation of ring-oscillator PUF.
J. Cryptogr. Eng., 2021

Model Reverse-Engineering Attack against Systolic-Array-Based DNN Accelerator Using Correlation Power Analysis.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

Adversarial Black-Box Attacks with Timing Side-Channel Leakage.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

Modeling attacks against device authentication using CMOS image sensor PUF.
IEICE Electron. Express, 2021

Towards Trusted IoT Sensing Systems: Implementing PUF as Secure Key Generator for Root of Trust and Message Authentication Code.
Proceedings of the HASP '21: Workshop on Hardware and Architectural Support for Security and Privacy, 2021

Deep Learning Side-Channel Attacks Against Lightweight SCA Countermeasure RSM-AES.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2021

Model Evasion Attacks Against Partially Encrypted Deep Neural Networks in Isolated Execution Environment.
Proceedings of the Applied Cryptography and Network Security Workshops, 2021

Towards Trained Model Confidentiality and Integrity Using Trusted Execution Environments.
Proceedings of the Applied Cryptography and Network Security Workshops, 2021

2020
Entropy Estimation of Physically Unclonable Functions.
IACR Cryptol. ePrint Arch., 2020

Model Reverse-Engineering Attack using Correlation Power Analysis against Systolic Array Based Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Cause Analysis Method of Entropy Loss in Physically Unclonable Functions.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Disabling Backdoor and Identifying Poison Data by using Knowledge Distillation in Backdoor Attacks on Deep Neural Networks.
Proceedings of the AISec@CCS 2020: Proceedings of the 13th ACM Workshop on Artificial Intelligence and Security, 2020

Exploring Effect of Residual Electric Charges on Cryptographic Circuits.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2019
Model-Extraction Attack Against FPGA-DNN Accelerator Utilizing Correlation Electromagnetic Analysis.
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Simple Electromagnetic Analysis Attacks based on Geometric Leak on an ASIC Implementation of Ring-Oscillator PUF.
Proceedings of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2019

2018
A Dynamic Soft-Decision Fuzzy Extractor for a CMOS Image Sensor PUF.
Proceedings of the 2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), 2018

2017
Hierarchical-Masked Image Filtering for Privacy-Protection.
IEICE Trans. Inf. Syst., 2017

Tamper-resistant cryptographic hardware.
IEICE Electron. Express, 2017

Malicious CAN-message attack against advanced driving assistant system.
Proceedings of the 2017 IEEE International Symposium on Hardware Oriented Security and Trust, 2017

2015
Reversing stealthy dopant-level circuits.
J. Cryptogr. Eng., 2015

Proposal of LED-based Peeping Prevention System.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Tamper-resistant authentication system with side-channel attack resistant AES and PUF using MDR-ROM.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Development of LED illumination-based spy photo-prevention system.
Proceedings of the IEEE 4th Global Conference on Consumer Electronics, 2015

2014
Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA.
ACM Trans. Reconfigurable Technol. Syst., 2014

On measurable side-channel leaks inside ASIC design primitives.
J. Cryptogr. Eng., 2014

Security Evaluation of RG-DTM PUF Using Machine Learning Attacks.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Unified Coprocessor Architecture for Secure Key Storage and Challenge-Response Authentication.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

Development of Compression Tolerable and Highly Implementable Watermarking Method for Mobile Devices.
IEICE Trans. Inf. Syst., 2014

Diffusion Programmable Device : The device to prevent reverse engineering.
IACR Cryptol. ePrint Arch., 2014

Live Demonstration: Hierarchical masked image filtering technology on security-camera for privacy protection.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Side-channel attack resistant AES cryptographic circuits with ROM reducing address-dependent EM leaks.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Interleaved-bitslice AES encryption and decryption with massive-parallel mobile embedded processor.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Development of effective information-hiding method for embedded systems.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Cipher-destroying and secret-key-emitting hardware Trojan against AES core.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

Hierarchical image-scrambling method with scramble-level controllability for privacy protection.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A stable key generation from PUF responses with a Fuzzy Extractor for cryptographic authentications.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

Hybrid masking using intra-masking dual-rail memory on LUT for SCA-Resistant AES implementation on FPGA (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2012
High Uniqueness Arbiter-Based PUF Circuit Utilizing RG-DTM Scheme for Identification and Authentication Applications.
IEICE Trans. Electron., 2012

Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

Intra-masking dual-rail memory on LUT implementation for tamper-resistant AES on FPGA.
Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Efficient DPA-Resistance Verification Method with Smaller Number of Power Traces on AES Cryptographic Circuit.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

2011
Placement Tool Dedicated for a Via-Programmable Logic Device VPEX.
Int. J. Comput. Their Appl., 2011

The arbiter-PUF with high uniqueness utilizing novel arbiter circuit with Delay-Time Measurement.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Implementation and verification of DPA-resistant cryptographic DES circuit using Domino-RSL.
Proceedings of the HOST 2011, 2011

2010
Placement Tool Dedicated for a Via-programmable Logic Device VPEX.
Proceedings of the ISCA 23rd International Conference on Computer Applications in Industry and Engineering, 2010

2008
Regular Fabric of Via Programmable Logic Device Using EXclusive-or Array (VPEX) for EB Direct Writing.
IEICE Trans. Electron., 2008

2007
Architecture of Via Programmable Logic using Exclusive-OR Array (VPEX) for EB Direct Writing.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2003
An embedded DRAM with a 143-MHz SRAM interface using a sense-synchronized read/write.
IEEE J. Solid State Circuits, 2003

A Low Power Embedded DRAM Macro for Battery-Operated LSIs.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

1997
A 1.2- to 3.3-V wide voltage-range/low-power DRAM with a charge-transfer presensing scheme.
IEEE J. Solid State Circuits, 1997


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