Mohamed Hassan

IEEE Trans. Computers, April, 2023

PISCOT: A Pipelined Split-Transaction COTS-Coherent Bus for Multi-Core Real-Time Systems.

[BibT_eX]

[DOI]

Salah Hessien

Abdelrhman Mohamed Abotaleb

ACM Trans. Embed. Comput. Syst., 2023

The Case for tinyML in Healthcare: CNNs for Real-Time On-Edge Blood Pressure Estimation.

[BibT_eX]

[DOI]

Bailian Sun

Safin Bayes

Francisco Javier Cazorla-Almeida

Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

Tracking Coherence-Related Contention Delays in Real-Time Multicore Systems.

[BibT_eX]

[DOI]

Proceedings of the 38th ACM/SIGAPP Symposium on Applied Computing, 2023

Improving Timing-Related Guarantees for Main Memory in Multicore Critical Embedded Systems.

[BibT_eX]

[DOI]

Asier Fernández de Lecea

Proceedings of the IEEE Real-Time Systems Symposium, 2023

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources.

[BibT_eX]

[DOI]

Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023

2022

tinyCare: A tinyML-based Low-Cost Continuous Blood Pressure Estimation on the Extreme Edge.

[BibT_eX]

[DOI]

Khaled Ahmed

Proceedings of the 10th IEEE International Conference on Healthcare Informatics, 2022

Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds.

[BibT_eX]

[DOI]

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

Predictably and Efficiently Integrating COTS Cache Coherence in Real-Time Systems.

[BibT_eX]

[DOI]

Mohamed Hossam

Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

2021

Designing Predictable Cache Coherence Protocols for Multi-Core Real-Time Systems.

[BibT_eX]

[DOI]

Anirudh Mohan Kaushik

IEEE Trans. Computers, 2021

DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.

[BibT_eX]

[DOI]

Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Duetto: Latency Guarantees at Minimal Performance Cost.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Reduced latency DRAM for multi-core safety-critical real-time systems.

[BibT_eX]

[DOI]

Real Time Syst., 2020

MCsim: An Extensible DRAM Memory Controller Simulator.

[BibT_eX]

[DOI]

IEEE Comput. Archit. Lett., 2020

The Best of All Worlds: Improving Predictability at the Performance of Conventional Coherence with No Protocol Modifications.

[BibT_eX]

[DOI]

Salah Hessien

Proceedings of the 41st IEEE Real-Time Systems Symposium, 2020

DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.

[BibT_eX]

[DOI]

Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

Analysis of Memory-Contention in Heterogeneous COTS MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

Discriminative Coherence: Balancing Performance and Latency Bounds in Data-Sharing Multi-Core Real-Time Systems.

[BibT_eX]

[DOI]

Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

2019

Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Real-Time Systems Symposium, 2019

Managing DRAM Interference in Mixed Criticality Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Microelectronics, 2019

2018

Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.

[BibT_eX]

[DOI]

Anirudh M. Kaushik

ACM Trans. Embed. Comput. Syst., 2018

A Comparative Study of Predictable DRAM Controllers.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2018

Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Heterogeneous MPSoCs for Mixed-Criticality Systems: Challenges and Opportunities.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

On the Off-Chip Memory Latency of Real-Time Systems: Is DDR DRAM Really the Best Option?

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

2017

Predictable Shared Memory Resources for Multi-Core Real-Time Systems.

[BibT_eX]

[DOI]

PhD thesis, 2017

PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2017

HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems.

[BibT_eX]

[DOI]

CoRR, 2017

Predictable Cache Coherence for Multi-core Real-Time Systems.

[BibT_eX]

[DOI]

Anirudh M. Kaushik

Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

2016

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

MCXplore: An automated framework for validating memory controller designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Reverse-engineering embedded memory controllers through latency-based analysis.

[BibT_eX]

[DOI]

Anirudh M. Kaushik