Hiren D. Patel

According to our database1, Hiren D. Patel authored at least 69 papers between 2004 and 2020.

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Bibliography

2020
On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core Architectures.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Enabling Predictable, Simultaneous and Coherent Data Sharing in Mixed Criticality Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

CARP: A Data Communication Mechanism for Multi-core Mixed-Criticality Systems.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

Strengthening PUFs using Composition.
Proceedings of the International Conference on Computer-Aided Design, 2019

2018
Exposing Implementation Details of Embedded DRAM Memory Controllers through Latency-based Analysis.
ACM Trans. Embed. Comput. Syst., 2018

A Comparative Study of Predictable DRAM Controllers.
ACM Trans. Embed. Comput. Syst., 2018

MCXplore: Automating the Validation Process of DRAM Memory Controller Designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

2017
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems.
ACM Trans. Embed. Comput. Syst., 2017

HourGlass: Predictable Time-based Cache Coherence Protocol for Dual-Critical Multi-Core Systems.
CoRR, 2017

Predictable Cache Coherence for Multi-core Real-Time Systems.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

2016
Path Selection for Real-Time Communication on Priority-Aware NoCs.
ACM Trans. Design Autom. Electr. Syst., 2016

Buffer Space Allocation for Real-Time Priority-Aware Networks.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Criticality- and Requirement-Aware Bus Arbitration for Multi-Core Mixed Criticality Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

MCXplore: An automated framework for validating memory controller designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
SLA: A Stage-Level Latency Analysisfor Real-Time Communicationin a Pipelined Resource Model.
IEEE Trans. Computers, 2015

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Reverse-engineering embedded memory controllers through latency-based analysis.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Static slack-based instrumentation of programs.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

2014
Reliable Computing with Ultra-Reduced Instruction Set Coprocessors.
IEEE Micro, 2014

A graph associated with the set of all nonzero annihilating ideals of a commutative ring.
Discret. Math. Algorithms Appl., 2014

MEMOCODE 2014 software design contest: Space Invaders emulator.
Proceedings of the Twelfth ACM/IEEE International Conference on Formal Methods and Models for Codesign, 2014

Bounding buffer space requirements for real-time priority-aware networks.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
An Instruction Scratchpad Memory Allocation for the Precision Timed Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2013

ORTAP: An Offset-based response time analysis for a pipelined communication resource model.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Systemc-clang: An open-source framework for analyzing mixed-abstraction SystemC models.
Proceedings of the 2013 Forum on specification and Design Languages, 2013

On the use of GP-GPUs for accelerating compute-intensive EDA applications.
Proceedings of the Design, Automation and Test in Europe, 2013

Low cost permanent fault detection using ultra-reduced instruction set co-processors.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
synASM: A High-Level Synthesis Framework With Support for Parallel and Timed Constructs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

Accelerating SystemC simulations using GPUs.
Proceedings of the 2012 IEEE International High Level Design Validation and Test Workshop, 2012

Reliable computing with ultra-reduced instruction set co-processors.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Parallel simulation of mixed-abstraction SystemC models on GPUs and multicore CPUs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

Using link-level latency analysis for path selection for real-time communication on NoCs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Robust heterogeneous data center design: a principled approach.
SIGMETRICS Perform. Evaluation Rev., 2011

An authorization scheme for version control systems.
Proceedings of the 16th ACM Symposium on Access Control Models and Technologies, 2011

Extending Force-Directed Scheduling with Explicit Parallel and Timed Constructs for High-Level Synthesis.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

Abstract state machines as an intermediate representation for high-level synthesis.
Proceedings of the Design, Automation and Test in Europe, 2011

Temporal isolation on multiprocessing architectures.
Proceedings of the 48th Design Automation Conference, 2011

PRET DRAM controller: bank privatization for predictability and temporal isolation.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Deploying Hard Real-Time Control Software on Chip-Multiprocessors.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

Towards a Multi-MoC Hardware/Software Co-design Framework Using Abstract State Machines.
Proceedings of the 11th International Workshop on Microprocessor Test and Verification, 2010

SCGPSim: a fast SystemC simulator on GPUs.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Generating Multi-Threaded code from Polychronous Specifications.
Electron. Notes Theor. Comput. Sci., 2009

A disruptive computer design idea: Architectures with repeatable timing.
Proceedings of the 27th International Conference on Computer Design, 2009

2008
On Cosimulating Multiple Abstraction-Level System-Level Models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Model-Driven Validation of SystemC Designs.
EURASIP J. Embed. Syst., 2008

SML-Sys: a functional framework with multiple models of computation for modeling heterogeneous system.
Design Autom. for Emb. Sys., 2008

On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications.
Proceedings of the 6th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2008), 2008

An Automated Mapping of Timed Functional Specification to a Precision Timed Architecture.
Proceedings of the 12th IEEE/ACM International Symposium on Distributed Simulation and Real-Time Applications, 2008

Predictable programming on a precision timed architecture.
Proceedings of the 2008 International Conference on Compilers, 2008

Exploring power management in multi-core systems.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Ingredients for Successful System Level Design Methodology.
Springer, ISBN: 978-1-4020-8471-3, 2008

2007
Ingredients for Successful System Level Automation & Design Methodology.
PhD thesis, 2007

EWD: A metamodeling driven customizable multi-MoC system modeling framework.
ACM Trans. Design Autom. Electr. Syst., 2007

Heterogeneous Behavioral Hierarchy Extensions for SystemC.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

Tackling an abstraction gap: co-simulating SystemC DE with bluespec ESL.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Performance modeling for early analysis of multi-core systems.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
CARH: service-oriented architecture for validating system-level designs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Deep vs. Shallow, Kernel vs. Language--What is Better for Heterogeneous Modeling in {SystemC}?.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design.
Proceedings of the 4th ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2006), 2006

Heterogeneous behavioral hierarchy for system level designs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
Design Issues for Networked Embedded Systems.
Proceedings of the Embedded Systems Handbook., 2005

Towards a heterogeneous simulation kernel for system-level models: a SystemC kernel for synchronous data flow models.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Automated Extraction of Structural Information from SystemC-based IP for Validation.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Towards Behavioural Hierarchy Extensions for SystemC.
Proceedings of the Forum on specification and Design Languages, 2005

Modelling Environment for Heterogeneous Systems based on MoCs.
Proceedings of the Forum on specification and Design Languages, 2005

SystemCXML: An Exstensible SystemC Front end Using XML.
Proceedings of the Forum on specification and Design Languages, 2005

An Introductory Survey of Networked Embedded Systems.
Proceedings of the Industrial Information Technology Handbook, 2005

2004
A Functional Programming Framework of Heterogeneous Model of Computation for System Design.
Proceedings of the Forum on specification and Design Languages, 2004

SystemC Kernel extensions for heterogeneous system modeling - a framework for multi-MoC modeling and simulation.
Kluwer, ISBN: 978-1-4020-8087-6, 2004


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