Francisco J. Cazorla

Affiliations:
  • Barcelona Supercomputing Center, Spain


According to our database1, Francisco J. Cazorla authored at least 219 papers between 2003 and 2022.

Collaborative distances:

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Bibliography

2022
ADBench: benchmarking autonomous driving systems.
Computing, 2022

2021
Worst-Case Energy Consumption: A New Challenge for Battery-Powered Critical Devices.
IEEE Trans. Sustain. Comput., 2021

Surrogate Applications for Early Design Stage Multicore Contention Modeling.
IEEE Trans. Emerg. Top. Comput., 2021

Towards functional safety compliance of matrix-matrix multiplication for machine learning-based autonomous systems.
J. Syst. Archit., 2021

Performance Analysis and Optimization Opportunities for NVIDIA Automotive GPUs.
J. Parallel Distributed Comput., 2021

MUCH: exploiting pairwise hardware event monitor correlations for improved timing analysis of complex MPSoCs.
Proceedings of the SAC '21: The 36th ACM/SIGAPP Symposium on Applied Computing, 2021

PRL: Standardizing Performance Monitoring Library for High-Integrity Real-Time Systems.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Demystifying the Characteristics of High Bandwidth Memory for Real-Time Systems.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Leveraging Hardware QoS to Control Contention in the Xilinx Zynq UltraScale+ MPSoC.
Proceedings of the 33rd Euromicro Conference on Real-Time Systems, 2021

Enabling Unit Testing of Already-Integrated AI Software Systems: The Case of Apollo for Autonomous Driving.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Empirical Evidence for MPSoCs in Critical Systems: The Case of NXP's T2080 Cache Coherence.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
GMAI: Understanding and Exploiting the Internals of GPU Resource Allocation in Critical Systems.
ACM Trans. Embed. Comput. Syst., 2020

HRM: Merging Hardware Event Monitors for Improved Timing Analysis of Complex MPSoCs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

GPU4S: Embedded GPUs in space - Latest project updates.
Microprocess. Microsystems, 2020

Multi-core Devices for Safety-critical Systems: A Survey.
ACM Comput. Surv., 2020

CleanET: enabling timing validation for complex automotive systems.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

IntPred: flexible, fast, and accurate object detection for autonomous driving systems.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

On the reliability of hardware event monitors in MPSoCs for critical domains.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

En-Route: on enabling resource usage testing for autonomous driving frameworks.
Proceedings of the SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30, 2020

Modeling Contention Interference in Crossbar-based Systems via Sequence-Aware Pairing (SeAP).
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

Timing of Autonomous Driving Software: Problem Analysis and Prospects for Future Solutions.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

A Cross-Layer Review of Deep Learning Frameworks to Ease Their Optimization and Reuse.
Proceedings of the 23rd IEEE International Symposium on Real-Time Distributed Computing, 2020

Tracing Hardware Monitors in the GR712RC Multicore Platform: Challenges and Lessons Learnt from a Space Case Study.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

UP2DATE: Safe and secure over-the-air software updates on high-performance mixed-criticality systems.
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020


An On-board Algorithm Implementation on an Embedded GPU: A Space Case Study.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Increasing the Reliability of Software Timing Analysis for Cache-Based Processors.
IEEE Trans. Computers, 2019

Locality-aware cache random replacement policies.
J. Syst. Archit., 2019

Time-Randomized Wormhole NoCs for Critical Applications.
ACM J. Emerg. Technol. Comput. Syst., 2019

Randomization for Safer, more Reliable and Secure, High-Performance Automotive Processors.
IEEE Des. Test, 2019

Probabilistic Worst-Case Timing Analysis: Taxonomy and Comprehensive Survey.
ACM Comput. Surv., 2019

ePAPI: Performance Application Programming Interface for Embedded Platforms.
Proceedings of the 19th International Workshop on Worst-Case Execution Time Analysis, 2019

Performance Analysis and Optimization of Automotive GPUs.
Proceedings of the 31st International Symposium on Computer Architecture and High Performance Computing, 2019

On assessing the viability of probabilistic scheduling with dependent tasks.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

Accurate ILP-Based Contention Modeling on Statically Scheduled Multicore Systems.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

STT-MRAM for real-time embedded systems: performance and WCET implications.
Proceedings of the International Symposium on Memory Systems, 2019

Software Timing Analysis for Complex Hardware with Survivability and Risk Analysis.
Proceedings of the 37th IEEE International Conference on Computer Design, 2019

Understanding and Exploiting the Internals of GPU Resource Allocation for Critical Systems.
Proceedings of the International Conference on Computer-Aided Design, 2019

Generating and Exploiting Deep Learning Variants to Increase Heterogeneous Resource Utilization in the NVIDIA Xavier.
Proceedings of the 31st Euromicro Conference on Real-Time Systems, 2019

Modeling the Impact of Process Variations in Worst-Case Energy Consumption Estimation.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

An Approach for Detecting Power Peaks During Testing and Breaking Systematic Pathological Behavior.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

GPU4S: Embedded GPUs in Space.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

AURIX TC277 Multicore Contention Model Integration for Automotive Applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Multicore Early Design Stage Guaranteed Performance Estimates for the Space Domain.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Maximum-Contention Control Unit (MCCU): Resource Access Count and Contention Time Enforcement.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

LAEC: Look-Ahead Error Correction Codes in Embedded Processors L1 Data Cache.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software Guidelines.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Towards limiting the impact of timing anomalies in complex real-time processors.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
Fitting Software Execution-Time Exceedance into a Residual Random Fault in ISO-26262.
IEEE Trans. Reliab., 2018

EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

High-Integrity Performance Monitoring Units in Automotive Chips for Reliable Timing V&V.
IEEE Micro, 2018

Safety-Related Challenges and Opportunities for GPUs in the Automotive Domain.
IEEE Micro, 2018

Probabilistic Load Flow Solution Considering Optimal Allocation of SVC in Radial Distribution System.
Int. J. Interact. Multim. Artif. Intell., 2018

Reconciling Time Predictability and Performance in Future Computing Systems.
IEEE Des. Test, 2018

Assessing Time Predictability Features of ARM Big. LITTLE Multicores.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

RPR: a random replacement policy with limited pathological replacements.
Proceedings of the 33rd Annual ACM Symposium on Applied Computing, 2018

NoCo: ILP-Based Worst-Case Contention Estimation for Mesh Real-Time Manycores.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

Industrial experiences with resource management under software randomization in ARINC653 avionics environments.
Proceedings of the International Conference on Computer-Aided Design, 2018

HWP: Hardware Support to Reconcile Cache Energy, Complexity, Performance and WCET Estimates in Multicore Real-Time Systems.
Proceedings of the 30th Euromicro Conference on Real-Time Systems, 2018

Design and integration of hierarchical-placement multi-level caches for real-time systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Cache side-channel attacks and time-predictability in high-performance critical real-time systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

Measurement-based cache representativeness on multipath programs.
Proceedings of the 55th Annual Design Automation Conference, 2018

Modelling multicore contention on the AURIX<sup><i>TM</i></sup> TC27x.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
Measurement-Based Worst-Case Execution Time Estimation Using the Coefficient of Variation.
ACM Trans. Design Autom. Electr. Syst., 2017

Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration.
IEEE Trans. Computers, 2017

Adapting TDMA arbitration for measurement-based probabilistic timing analysis.
Microprocess. Microsystems, 2017

Execution time distributions in embedded safety-critical systems using extreme value theory.
Int. J. Data Anal. Tech. Strateg., 2017

On the assessment of probabilistic WCET estimates reliability for arbitrary programs.
EURASIP J. Embed. Syst., 2017

Modelling bus contention during system early design stages.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

On uses of extreme value theory fit for industrial-quality WCET analysis.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

On the tailoring of CAST-32A certification guidance to real COTS multicore architectures.
Proceedings of the 12th IEEE International Symposium on Industrial Embedded Systems, 2017

SEDEA: A Sensible Approach to Account DRAM Energy in Multicore Systems.
Proceedings of the 29th International Symposium on Computer Architecture and High Performance Computing, 2017

Work-in-Progress Paper: An Analysis of the Impact of Dependencies on Probabilistic Timing Analysis and Task Scheduling.
Proceedings of the 2017 IEEE Real-Time Systems Symposium, 2017

EPC Enacted: Integration in an Industrial Toolbox and Use against a Railway Application.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

Design and Implementation of a Time Predictable Processor: Evaluation With a Space Case Study.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Boosting Guaranteed Performance in Wormhole NoCs with Probabilistic Timing Analysis.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Design and implementation of a fair credit-based bandwidth sharing scheme for buses.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Probabilistic timing analysis on time-randomized platforms for the space domain.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Dynamic software randomisation: Lessons learnec from an aerospace case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Software Time Reliability in the Presence of Cache Memories.
Proceedings of the Reliable Software Technologies - Ada-Europe 2017, 2017

MC2: Multicore and Cache Analysis via Deterministic and Probabilistic Jitter Bounding.
Proceedings of the Reliable Software Technologies - Ada-Europe 2017, 2017

2016
DReAM: An Approach to Estimate per-Task DRAM Energy in Multicore Systems.
ACM Trans. Design Autom. Electr. Syst., 2016

Parallelizing Industrial Hard Real-Time Applications for the parMERASA Multicore.
ACM Trans. Embed. Comput. Syst., 2016

Thread Assignment in Multicore/Multithreaded Processors: A Statistical Approach.
IEEE Trans. Computers, 2016

Sensible Energy Accounting with Abstract Metering for Multicore Systems.
ACM Trans. Archit. Code Optim., 2016

Fitting processor architectures for measurement-based probabilistic timing analysis.
Microprocess. Microsystems, 2016

Measurement-Based Timing Analysis of the AURIX Caches.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Mitigating Software-Instrumentation Cache Effects in Measurement-Based Timing Analysis.
Proceedings of the 16th International Workshop on Worst-Case Execution Time Analysis, 2016

Data Bus Slicing for Contention-Free Multicore Real-Time Memory Systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Contention-aware performance monitoring counte support for real-time MPSoCs.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Modelling the confidence of timing analysis for time randomised caches.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

Automotive Safety Concept Definition for Mixed-Criticality Integration on a COTS Multicore.
Proceedings of the Computer Safety, Reliability, and Security, 2016

Improving Early Design Stage Timing Modeling in Multicore Based Real-Time Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Modeling High-Performance Wormhole NoCs for Critical Real-Time Embedded Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Modelling Probabilistic Cache Representativeness in the Presence of Arbitrary Access Patterns.
Proceedings of the 19th IEEE International Symposium on Real-Time Distributed Computing, 2016

Resilient random modulo cache memories for probabilistically-analyzable real-time systems.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

A confidence assessment of WCET estimates for software time randomized caches.
Proceedings of the 14th IEEE International Conference on Industrial Informatics, 2016

TASA: toolchain-agnostic static software randomisation for critical real-time systems.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

pTNoC: Probabilistically Time-Analyzable Tree-Based NoC for Mixed-Criticality Systems.
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016


Improving performance guarantees in wormhole mesh NoC designs.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Supertask: Maximizing runnable-level parallelism in AUTOSAR applications.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Random modulo: a new processor cache design for real-time critical systems.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Randomized Caches Can Be Pretty Useful to Hard Real-Time Systems.
Leibniz Trans. Embed. Syst., 2015

WCET analysis methods: Pitfalls and challenges on their trustworthiness.
Proceedings of the 10th IEEE International Symposium on Industrial Embedded Systems, 2015

Introduction to partial time composability for COTS multicores.
Proceedings of the 30th Annual ACM Symposium on Applied Computing, 2015

EPC: Extended Path Coverage for Measurement-Based Probabilistic Timing Analysis.
Proceedings of the 2015 IEEE Real-Time Systems Symposium, 2015

Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors.
Proceedings of the IEEE 18th International Symposium on Real-Time Distributed Computing, 2015

Increasing multicore system efficiency through intelligent bandwidth shifting.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

CAP: Communication-Aware Allocation Algorithm for Real-Time Parallel Applications on Many-Cores.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Enabling TDMA Arbitration in the Context of MBPTA.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

IEC-61508 SIL 3 Compliant Pseudo-Random Number Generators for Probabilistic Timing Analysis.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Timing analysis of an avionics case study on complex hardware/software platforms.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

PACO: fast average-performance estimation for time-randomized caches.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Resource usage templates and signatures for COTS multicore processors.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Increasing confidence on measurement-based contention bounds for real-time round-robin buses.
Proceedings of the 52nd Annual Design Automation Conference, 2015

Speeding up Static Probabilistic Timing Analysis.
Proceedings of the Architecture of Computing Systems - ARCS 2015, 2015

A Safety Concept for a Railway Mixed-Criticality Embedded System Based on Multicore Partitioning.
Proceedings of the 15th IEEE International Conference on Computer and Information Technology, 2015

2014
Adaptive Prefetching on POWER7: Improving Performance and Power Consumption.
ACM Trans. Parallel Comput., 2014

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation.
ACM Trans. Design Autom. Electr. Syst., 2014

Efficient Cache Designs for Probabilistically Analysable Real-Time Systems.
IEEE Trans. Computers, 2014

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments.
IEEE Micro, 2014

Per-task Energy Accounting in Computing Systems.
IEEE Comput. Archit. Lett., 2014

Contention in Multicore Hardware Shared Resources: Understanding of the State of the Art.
Proceedings of the 14th International Workshop on Worst-Case Execution Time Analysis, 2014

A Dual-Criticality Memory Controller (DCmc): Proposal and Evaluation of a Space Case Study.
Proceedings of the IEEE 35th IEEE Real-Time Systems Symposium, 2014

AHRB: A high-performance time-composable AMBA AHB bus.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

DReAM: Per-Task DRAM Energy Metering in Multicore Systems.
Proceedings of the Euro-Par 2014 Parallel Processing, 2014

Parallel many-core avionics systems.
Proceedings of the 2014 International Conference on Embedded Software, 2014

PUB: Path Upper-Bounding for Measurement-Based Probabilistic Timing Analysis.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

Heart of Gold: Making the Improbable Happen to Increase Confidence in MBPTA.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

On the Comparison of Deterministic and Probabilistic WCET Estimation Techniques.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

Measurement-Based Probabilistic Timing Analysis and Its Impact on Processor Architecture.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Bus designs for time-probabilistic multicore processors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Time-Analysable Non-Partitioned Shared Caches for Real-Time Multicore Systems.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Containing Timing-Related Certification Cost in Automotive Systems Deploying Complex Hardware.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

RunPar: An allocation algorithm for automotive applications exploiting runnable parallelism in multicores.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
Thread Assignment of Multithreaded Network Applications in Multicore/Multithreaded Processors.
IEEE Trans. Parallel Distributed Syst., 2013

Timing effects of DDR memory systems in hard real-time multicore architectures: Issues and solutions.
ACM Trans. Embed. Comput. Syst., 2013

A hard real-time capable multi-core SMT processor.
ACM Trans. Embed. Comput. Syst., 2013

PROARTIS: Probabilistically Analyzable Real-Time Systems.
ACM Trans. Embed. Comput. Syst., 2013

SMT Malleability in IBM POWER5 and POWER6 Processors.
IEEE Trans. Computers, 2013

Fair CPU time accounting in CMP+SMT processors.
ACM Trans. Archit. Code Optim., 2013

Hardware support for accurate per-task energy metering in multicore systems.
ACM Trans. Archit. Code Optim., 2013

Applying Measurement-Based Probabilistic Timing Analysis to Buffer Resources.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013

Upper-bounding Program Execution Time with Extreme Value Theory.
Proceedings of the 13th International Workshop on Worst-Case Execution Time Analysis, 2013

Measurement-based probabilistic timing analysis: Lessons from an integrated-modular avionics case study.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Deconstructing bus access control policies for Real-Time multicores.
Proceedings of the 8th IEEE International Symposium on Industrial Embedded Systems, 2013

Multi-level Unified Caches for Probabilistically Time Analysable Real-Time Systems.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

On-chip ring network designs for hard-real time systems.
Proceedings of the 21st International Conference on Real-Time Networks and Systems, 2013

Achieving timing composability with measurement-based probabilistic timing analysis.
Proceedings of the 16th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2013

DTM: Degraded Test Mode for Fault-Aware Probabilistic Timing Analysis.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013


Probabilistic timing analysis on conventional cache designs.
Proceedings of the Design, Automation and Test in Europe, 2013

A cache design for probabilistically analysable real-time systems.
Proceedings of the Design, Automation and Test in Europe, 2013

On the convergence of mainstream and mission-critical markets.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
CPU Accounting for Multicore Processors.
IEEE Trans. Computers, 2012

On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments.
ACM Trans. Archit. Code Optim., 2012

Kernel Partitioning of Streaming Applications: A Statistical Approach to an NP-complete Problem.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

Characterizing thread placement in the IBM POWER7 processor.
Proceedings of the 2012 IEEE International Symposium on Workload Characterization, 2012

Assessing the suitability of the NGMP multi-core processor in the space domain.
Proceedings of the 12th International Conference on Embedded Software, 2012

Measurement-Based Probabilistic Timing Analysis for Multi-path Programs.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

Optimal task assignment in multithreaded processors: a statistical approach.
Proceedings of the 17th International Conference on Architectural Support for Programming Languages and Operating Systems, 2012

Making data prefetch smarter: adaptive prefetching on POWER7.
Proceedings of the International Conference on Parallel Architectures and Compilation Techniques, 2012

2011
Dynamic Cache Partitioning Based on the MLP of Cache Misses.
Trans. High Perform. Embed. Archit. Compil., 2011

Exploiting intra-task slack time of load operations for DVFS in hard real-time multi-core systems.
SIGBED Rev., 2011

Energy-Aware Accounting and Billing in Large-Scale Computing Facilities.
IEEE Micro, 2011

Characterizing Power and Temperature Behavior of POWER6-Based System.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

IA^3: An Interference Aware Allocation Algorithm for Multicore Hard Real-Time Systems.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

A Software-Pipelined Approach to Multicore Execution of Timing Predictable Multi-threaded Hard Real-Time Tasks.
Proceedings of the 14th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2011

A Quantitative Analysis of OS Noise.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

RVC-based time-predictable faulty caches for safety-critical systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

Towards improved survivability in safety-critical systems.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

RVC: a mechanism for time-analyzable real-time processors with faulty caches.
Proceedings of the High Performance Embedded Architectures and Compilers, 2011

Hybrid high-performance low-power and ultra-low energy reliable caches.
Proceedings of the 8th Conference on Computing Frontiers, 2011

2010
On the Problem of Evaluating the Performance of Multiprogrammed Workloads.
IEEE Trans. Computers, 2010

Merasa: Multicore Execution of Hard Real-Time Applications Supporting Analyzability.
IEEE Micro, 2010

Trends and techniques for energy efficient architectures.
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

Thread to strand binding of parallel network applications in massive multi-threaded systems.
Proceedings of the 15th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2010

Adapting cache partitioning algorithms to pseudo-LRU replacement policies.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Power and performance aware reconfigurable cache for CMPs.
Proceedings of the Second International Forum on Next-Generation Multicore/Manycore Technologies, 2010

Load balancing using dynamic cache allocation.
Proceedings of the 7th Conference on Computing Frontiers, 2010

Power and thermal characterization of POWER6 system.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
FlexDCP: a QoS framework for CMP architectures.
ACM SIGOPS Oper. Syst. Rev., 2009

An Analyzable Memory Controller for Hard Real-Time CMPs.
IEEE Embed. Syst. Lett., 2009

CPU Accounting in CMP Processors.
IEEE Comput. Archit. Lett., 2009

Thread to Core Assignment in SMT On-Chip Multiprocessors.
Proceedings of the 21st International Symposium on Computer Architecture and High Performance Computing, 2009

Characterizing the resource-sharing levels in the UltraSPARC T2 processor.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Hardware support for WCET analysis of hard real-time multicore systems.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Using Randomized Caches in Probabilistic Real-Time Systems.
Proceedings of the 21st Euromicro Conference on Real-Time Systems, 2009

ITCA: Inter-task Conflict-Aware CPU Accounting for CMPs.
Proceedings of the PACT 2009, 2009

2008
Multicore Resource Management.
IEEE Micro, 2008

A dynamic scheduler for balancing HPC applications.
Proceedings of the ACM/IEEE Conference on High Performance Computing, 2008

Measuring Operating System Overhead on CMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

Selection of the Register File Size and the Resource Allocation Policy on SMT Processors.
Proceedings of the 20th International Symposium on Computer Architecture and High Performance Computing, 2008

A Two-Level Load/Store Queue Based on Execution Locality.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Software-Controlled Priority Characterization of POWER5 Processor.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Balancing HPC applications through smart allocation of resources in MT processors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

MFLUSH: Handling Long-Latency Loads in SMT On-Chip Multiprocessors.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Architecture Performance Prediction Using Evolutionary Artificial Neural Networks.
Proceedings of the Applications of Evolutionary Computing, 2008

Evolutionary system for prediction and optimization of hardware architecture performance.
Proceedings of the IEEE Congress on Evolutionary Computation, 2008

Soft Real-Time Scheduling on SMT Processors with Explicit Resource Allocation.
Proceedings of the Architecture of Computing Systems, 2008

2007
Explaining Dynamic Cache Partitioning Speed Ups.
IEEE Comput. Archit. Lett., 2007

Online Prediction of Applications Cache Utility.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

On the Problem of Minimizing Workload Execution Time in SMT Processors.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007

FAME: FAirly MEasuring Multithreaded Architectures.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

A Flexible Heterogeneous Multi-Core Architecture.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

MLP-Aware Dynamic Cache Partitioning.
Proceedings of the 16th International Conference on Parallel Architectures and Compilation Techniques (PACT 2007), 2007

2006
Predictable Performance in SMT Processors: Synergy between the OS and SMTs.
IEEE Trans. Computers, 2006

2005
Kilo-Instruction Processors: Overcoming the Memory Wall.
IEEE Micro, 2005

Architectural support for real-time task scheduling in SMT processors.
Proceedings of the 2005 International Conference on Compilers, 2005

2004
QoS for High-Performance SMT Processors in Embedded Systems.
IEEE Micro, 2004

Optimising long-latency-load-aware fetch policies for SMT processors.
Int. J. High Perform. Comput. Netw., 2004

Dynamically Controlled Resource Allocation in SMT Processors.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

DCache Warn: An I-Fetch Policy to Increase SMT Efficiency.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Enabling SMT for real-time embedded systems.
Proceedings of the 2004 12th European Signal Processing Conference, 2004

Feasibility of QoS for SMT.
Proceedings of the Euro-Par 2004 Parallel Processing, 2004

Implicit vs. Explicit Resource Allocation in SMT Processors.
Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Predictable performance in SMT processors.
Proceedings of the First Conference on Computing Frontiers, 2004

2003
Improving Memory Latency Aware Fetch Policies for SMT Processors.
Proceedings of the High Performance Computing, 5th International Symposium, 2003


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