Rodolfo Pellizzoni

Orcid: 0000-0002-7331-804X

Affiliations:
  • University of Waterloo, Canada


According to our database1, Rodolfo Pellizzoni authored at least 105 papers between 2004 and 2023.

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Bibliography

2023
Lazy Load Scheduling for Mixed-criticality Applications in Heterogeneous MPSoCs.
ACM Trans. Embed. Comput. Syst., 2023

X-Stream: Accelerating streaming segments on MPSoCs for real-time applications.
J. Syst. Archit., 2023

Co-Optimizing Cache Partitioning and Multi-Core Task Scheduling: Exploit Cache Sensitivity or Not?
Proceedings of the IEEE Real-Time Systems Symposium, 2023

A Tight Holistic Memory Latency Bound Through Coordinated Management of Memory Resources.
Proceedings of the 35th Euromicro Conference on Real-Time Systems, 2023

2022
HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators.
ACM Trans. Reconfigurable Technol. Syst., 2022

Beyond Just Safety: Delay-aware Security Monitoring for Real-time Control Systems.
ACM Trans. Cyber Phys. Syst., 2022

Parallelism-Aware High-Performance Cache Coherence with Tight Latency Bounds.
Proceedings of the 34th Euromicro Conference on Real-Time Systems, 2022

Optimizing parallel PREM compilation over nested loop structures.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
An Analyzable Inter-core Communication Framework for High-Performance Multicore Embedded Systems.
J. Syst. Archit., 2021

A Real-Time Virtio-Based Framework for Predictable Inter-VM Communication.
Proceedings of the 42nd IEEE Real-Time Systems Symposium, 2021

Worst-case latency analysis for the versal NoC network packet switch.
Proceedings of the NOCS '21: International Symposium on Networks-on-Chip, 2021

DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance.
Proceedings of the MEMSYS 2021: The International Symposium on Memory Systems, Washington, USA, September 27, 2021

Duetto: Latency Guarantees at Minimal Performance Cost.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Virtual Gang Scheduling of Parallel Real-Time Tasks.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020
HopliteBuf: Network Calculus-Based Design of FPGA NoCs with Provably Stall-Free FIFOs.
ACM Trans. Reconfigurable Technol. Syst., 2020

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

On Scheduler Side-Channels in Dynamic-Priority Real-Time Systems.
CoRR, 2020

MCsim: An Extensible DRAM Memory Controller Simulator.
IEEE Comput. Archit. Lett., 2020

DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining.
Proceedings of the IEEE Real-Time and Embedded Technology and Applications Symposium, 2020

SCE-Comm: A Real-Time Inter-Core Communication Framework for Strictly Partitioned Multi-core Processors.
Proceedings of the 9th Mediterranean Conference on Embedded Computing, 2020

Learn the Switches: Evolving FPGA NoCs with Stall-Free and Backpressure Based Routers.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Analysis of Memory-Contention in Heterogeneous COTS MPSoCs.
Proceedings of the 32nd Euromicro Conference on Real-Time Systems, 2020

Period Adaptation for Continuous Security Monitoring in Multicore Real-Time Systems.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
A real-time scratchpad-centric OS with predictable inter/intra-core communication for multi-core embedded systems.
Real Time Syst., 2019

Segment Streaming for the Three-Phase Execution Model: Design and Implementation.
Proceedings of the IEEE Real-Time Systems Symposium, 2019

Bundled Scheduling of Parallel Real-Time Tasks.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

A Novel Side-Channel in Real-Time Schedulers.
Proceedings of the 25th IEEE Real-Time and Embedded Technology and Applications Symposium, 2019

HopliteBuf: FPGA NoCs with Provably Stall-Free FIFOs.
Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

PREM-Based Optimal Task Segmentation Under Fixed Priority Scheduling.
Proceedings of the 31st Euromicro Conference on Real-Time Systems, 2019

Designing Mixed Criticality Applications on Modern Heterogeneous MPSoC Platforms.
Proceedings of the 31st Euromicro Conference on Real-Time Systems, 2019

2018
A Comparative Study of Predictable DRAM Controllers.
ACM Trans. Embed. Comput. Syst., 2018

Bounding DRAM Interference in COTS Heterogeneous MPSoCs for Mixed Criticality Systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

ScheduLeak: A Novel Scheduler Side-Channel Attack Against Real-Time Autonomous Control Systems.
CoRR, 2018

Analysis of Dynamic Memory Bandwidth Regulation in Multi-core Real-Time Systems.
Proceedings of the 2018 IEEE Real-Time Systems Symposium, 2018

A design-space exploration for allocating security tasks in multicore real-time systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
PMC: A Requirement-Aware DRAM Controller for Multicore Mixed Criticality Systems.
ACM Trans. Embed. Comput. Syst., 2017

A Reconnaissance Attack Mechanism for Fixed-Priority Real-Time Systems.
CoRR, 2017

A Reliable and Predictable Scratchpad-centric OS for Multi-core Embedded Systems.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

A Requests Bundling DRAM Controller for Mixed-Criticality Systems.
Proceedings of the 2017 IEEE Real-Time and Embedded Technology and Applications Symposium, 2017

HopliteRT: An efficient FPGA NoC for real-time applications.
Proceedings of the International Conference on Field Programmable Technology, 2017

WCET-Driven Dynamic Data Scratchpad Management With Compiler-Directed Prefetching.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Contego: An Adaptive Framework for Integrating Security Tasks in Real-Time Systems.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

WCET Derivation under Single Core Equivalence with Explicit Memory Budget Assignment.
Proceedings of the 29th Euromicro Conference on Real-Time Systems, 2017

Modeling the Effects of AUTOSAR Overheads on Application Timing and Schedulability.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
Memory Bandwidth Management for Efficient Performance Isolation in Multi-Core Platforms.
IEEE Trans. Computers, 2016

Schedulability Analysis for Memory Bandwidth Regulated Multicore Real-Time Systems.
IEEE Trans. Computers, 2016

Global Real-Time Memory-Centric Scheduling for Multicore Systems.
IEEE Trans. Computers, 2016

A composable worst case latency analysis for multi-rank DRAM devices under open row policy.
Real Time Syst., 2016

Integrating security constraints into fixed priority real-time schedulers.
Real Time Syst., 2016

Real-Time Computing on Multicore Processors.
Computer, 2016

Exploring Opportunistic Execution for Integrating Security into Legacy Hard Real-Time Systems.
Proceedings of the 2016 IEEE Real-Time Systems Symposium, 2016

A Real-Time Scratchpad-Centric OS for Multi-Core Embedded Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Memory Servers for Multicore Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

Trading Cores for Memory Bandwidth in Real-Time Systems.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

2015
A Survey on Cache Management Mechanisms for Real-Time Embedded Systems.
ACM Comput. Surv., 2015

A generalized model for preventing information leakage in hard real-time systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

A framework for scheduling DRAM memory accesses for multi-core mixed-time critical systems.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Memory efficient global scheduling of real-time tasks.
Proceedings of the 21st IEEE Real-Time and Embedded Technology and Applications Symposium, 2015

Generation of communication schedules using component interfaces.
Proceedings of the 20th IEEE Conference on Emerging Technologies & Factory Automation, 2015

Parallelism-Aware Memory Interference Delay Analysis for COTS Multicore Systems.
Proceedings of the 27th Euromicro Conference on Real-Time Systems, 2015

WCET(m) Estimation in Multi-core Systems Using Single Core Equivalence.
Proceedings of the 27th Euromicro Conference on Real-Time Systems, 2015

2014
A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets.
Real Time Syst., 2014

PALLOC: DRAM bank-aware memory allocator for performance isolation on multicore platforms.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Hiding memory latency using fixed priority scheduling.
Proceedings of the 20th IEEE Real-Time and Embedded Technology and Applications Symposium, 2014

Schedulability analysis of global memory-predictable scheduling.
Proceedings of the 2014 International Conference on Embedded Software, 2014

Real-Time Systems Security through Scheduler Constraints.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

A Rank-Switching, Open-Row DRAM Controller for Time-Predictable Systems.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

Generation of communication schedules for multi-mode distributed real-time applications.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Time-predictable execution of multithreaded applications on multicore systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Real-Time I/O Management System with COTS Peripherals.
IEEE Trans. Computers, 2013

Implementation and evaluation of global and partitioned scheduling in a real-time OS.
Real Time Syst., 2013

Worst Case Analysis of DRAM Latency in Multi-requestor Systems.
Proceedings of the IEEE 34th Real-Time Systems Symposium, 2013

MemGuard: Memory bandwidth reservation system for efficient performance isolation in multi-core platforms.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

Real-time cache management framework for multi-core architectures.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

ORTAP: An Offset-based response time analysis for a pipelined communication resource model.
Proceedings of the 19th IEEE Real-Time and Embedded Technology and Applications Symposium, 2013

A Dynamic Scratchpad Memory Unit for Predictable Real-Time Embedded Systems.
Proceedings of the 25th Euromicro Conference on Real-Time Systems, 2013

2012
Modeling towards incremental early analyzability of networked avionics systems using virtual integration.
ACM Trans. Embed. Comput. Syst., 2012

Real-Time Scheduling of Concurrent Transactions in Multidomain Ring Buses.
IEEE Trans. Computers, 2012

Memory-centric scheduling for multicore hard real-time systems.
Real Time Syst., 2012

Memory-Aware Scheduling of Multicore Task Sets for Real-Time Systems.
Proceedings of the 2012 IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2012

Memory Access Control in Multiprocessor for Real-Time Systems with Mixed Criticality.
Proceedings of the 24th Euromicro Conference on Real-Time Systems, 2012

2011
A Slot-Based Real-Time Scheduling Algorithm for Concurrent Transactions in NoC.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Timing Analysis for Resource Access Interference on Adaptive Resource Arbiters.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

A Predictable Execution Model for COTS-Based Embedded Systems.
Proceedings of the 17th IEEE Real-Time and Embedded Technology and Applications Symposium, 2011

2010
Predictable and monitored execution for COTS-based real-time embedded systems
PhD thesis, 2010

Impact of Peripheral-Processor Interference on WCET Analysis of Real-Time Embedded Systems.
IEEE Trans. Computers, 2010

Real-Time Communication for Multicore Systems with Multi-domain Ring Buses.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

Worst case delay analysis for memory interference in multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2010

Worst-case response time analysis of resource access models in multi-core systems.
Proceedings of the 47th Design Automation Conference, 2010

2009
Rapid Early-Phase Virtual Integration.
Proceedings of the 30th IEEE Real-Time Systems Symposium, 2009

Real-Time Control of I/O COTS Peripherals for Embedded Systems.
Proceedings of the 30th IEEE Real-Time Systems Symposium, 2009

ASIIST: Application Specific I/O Integration Support Tool for Real-Time Bus Architecture Designs.
Proceedings of the 14th IEEE International Conference on Engineering of Complex Computer Systems, 2009

Handling mixed-criticality in SoC-based real-time embedded systems.
Proceedings of the 9th ACM & IEEE International conference on Embedded software, 2009

2008
M-CASH: A real-time resource reclaiming algorithm for multiprocessor platforms.
Real Time Syst., 2008

Hardware Runtime Monitoring for Dependable COTS-Based Real-Time Embedded Systems.
Proceedings of the 29th IEEE Real-Time Systems Symposium, 2008

Coscheduling of CPU and I/O Transactions in COTS-Based Embedded Systems.
Proceedings of the 29th IEEE Real-Time Systems Symposium, 2008

Hybrid Hardware-Software Architecture for Reconfigurable Real-Time Systems.
Proceedings of the 14th IEEE Real-Time and Embedded Technology and Applications Symposium, 2008

2007
Real-Time Management of Hardware and Software Tasks for FPGA-based Embedded Systems.
IEEE Trans. Computers, 2007

Holistic analysis of asynchronous real-time transactions with earliest deadline scheduling.
J. Comput. Syst. Sci., 2007

Toward the Predictable Integration of Real-Time COTS Based Systems.
Proceedings of the 28th IEEE Real-Time Systems Symposium (RTSS 2007), 2007

Soft Real-Time Chains for Multi-Hop Wireless Ad-Hoc Networks.
Proceedings of the 13th IEEE Real-Time and Embedded Technology and Applications Symposium, 2007

2006
Adaptive Allocation of Software and Hardware Real-Time Tasks for FPGA-based Embedded Systems.
Proceedings of the 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), 2006

2005
Feasibility Analysis of Real-Time Periodic Tasks with Offsets.
Real Time Syst., 2005

Improved Schedulability Analysis of Real-Time Transactions with Earliest Deadline Scheduling.
Proceedings of the 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 2005

2004
A New Sufficient Feasibility Test for Asynchronous Real-Time Periodic Task Sets.
Proceedings of the 16th Euromicro Conference on Real-Time Systems (ECRTS 2004), 30 June, 2004


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