Ahmed M. Eltawil

According to our database1, Ahmed M. Eltawil authored at least 155 papers between 2002 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
Effect of Sensor Error on the Assessment of Seismic Building Damage.
IEEE Trans. Instrumentation and Measurement, 2020

Application of ICA on Self-Interference Cancellation of In-band Full Duplex Systems.
CoRR, 2020

2019
Power Performance Tradeoffs Using Adaptive Bit Width Adjustments on Resistive Associative Processors.
IEEE Trans. on Circuits and Systems, 2019

Hybrid pyramid-DWT-SVD dual data hiding technique for videos ownership protection.
Multimedia Tools Appl., 2019

Error-triggered Three-Factor Learning Dynamics for Crossbar Arrays.
CoRR, 2019

Spiking Neural Networks for Inference and Learning: A Memristor-based Design Perspective.
CoRR, 2019

Power Consumption and Energy-Efficiency for In-Band Full-Duplex Wireless Systems.
CoRR, 2019

Non-Stationary Polar Codes for Resistive Memories.
CoRR, 2019

Performance Analysis and Enhancements for In-Band Full-Duplex Wireless Local Area Networks.
CoRR, 2019

On Resistive Memories: One Step Row Readout Technique and Sensing Circuitry.
CoRR, 2019

IBCFAP: Intra-Body Communications Five-Layers Arm Phantom Model.
IEEE Access, 2019

Feasibility Study of Plant Health Monitoring.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Testing Topology Adaptive Irrigation IoT with Circuits.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Simple MOS Transistor-Based Realization of Fractional-Order Capacitors.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Sensitivity of Galvanic Intra-Body Communication Channel to System Parameters.
Proceedings of the Body Area Networks. Smart IoT and Big Data for Intelligent Health Management, 2019

2018
Active Cancellation of Self-Interference for Full-Duplex Amplify and Forward Wi-Fi Relay.
IEEE Wireless Commun. Letters, 2018

A Two-Dimensional Associative Processor.
IEEE Trans. VLSI Syst., 2018

Modeling and Analysis of Passive Switching Crossbar Arrays.
IEEE Trans. on Circuits and Systems, 2018

Power optimization techniques for associative processors.
Journal of Systems Architecture - Embedded Systems Design, 2018

Scheduling and power adaptation for wireless local area networks with full-duplex capability.
Trans. Emerging Telecommunications Technologies, 2018

A Hybrid Approximate Computing Approach for Associative In-Memory Processors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Physical Multi-Layer Phantoms for Intra-Body Communications.
IEEE Access, 2018

Overcoming Crossbar Nonidealities in Binary Neural Networks Through Learning.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Minimal Disturbed Bits in Writing Resistive Crossbar Memories.
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

Low-Power Resistive Associative Processor Implementation Through the Multi-Compare.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Collision Tolerance and Throughput Gain in Full-Duplex IEEE 802.11 DCF.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

Circuit Inspired Modeling Method for Irrigation.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

Rapid in-memory matrix multiplication using associative processor.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Extracting the Cole-Cole Model Parameters of Tissue-mimicking Materials.
Proceedings of the 2018 IEEE Biomedical Circuits and Systems Conference, 2018

Robust Frame Boundary Synchronization for In-Band Full-Duplex OFDM System.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017
Microarchitecture-Level SoC Design.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

Practical Framework for Downlink MU-MIMO for LTE Systems.
IEEE Wireless Commun. Letters, 2017

Approximate Memristive In-memory Computing.
ACM Trans. Embedded Comput. Syst., 2017

Reliability Enhancement of Low-Power Sequential Circuits Using Reconfigurable Pulsed Latches.
IEEE Trans. on Circuits and Systems, 2017

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement.
IET Circuits, Devices & Systems, 2017

A Simple Full-Duplex MAC Protocol Exploiting Asymmetric Traffic Loads in WiFi Systems.
Proceedings of the 2017 IEEE Wireless Communications and Networking Conference, 2017

Low Latency Approximate Adder for Highly Correlated Input Streams.
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017

Frequency and Timing Synchronization for In-Band Full-Duplex OFDM System.
Proceedings of the 2017 IEEE Global Communications Conference, 2017

Efficient pulsed-latch implementation for multiport register files: work-in-progress.
Proceedings of the 2017 International Conference on Compilers, 2017

3D mesh robust watermarking technique for ownership protection.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016
A case study to develop a graduate-level degree program in embedded & cyber-physical systems.
SIGBED Review, 2016

Dynamic Resource Management in High Throughput Satellite with Multi Port Amplifier (MPA).
IJITN, 2016

Performance analysis of full-duplex multiuser decode-and-forward relay networks with interference management.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2016

A System-Level Exploration of Power Delivery Architectures for Near-Threshold Manycores Considering Performance Constraints.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Poster Abstract: Unifying Modeling Substrate for Irrigation Cyber-Physical Systems.
Proceedings of the 7th ACM/IEEE International Conference on Cyber-Physical Systems, 2016

Process variations-aware resistive associative processor design.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

Erratum to: Chapter 4 Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

Resizable Data Composer (RDC) Cache: A Near-Threshold Cache Tolerating Process Variation via Architectural Fault Tolerance.
Proceedings of the Near Threshold Computing, Technology, Methods and Applications., 2016

2015
Full-Duplex Systems Using Multireconfigurable Antennas.
IEEE Trans. Wireless Communications, 2015

All-Digital Self-Interference Cancellation Technique for Full-Duplex Systems.
IEEE Trans. Wireless Communications, 2015

On Phase Noise Suppression in Full-Duplex Systems.
IEEE Trans. Wireless Communications, 2015

Energy Aware Mapping for Reconfigurable Wireless MPSoCs.
IEEE Trans. VLSI Syst., 2015

DWT-based watermarking technique for video authentication.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015

Advanced base station precoding and user receiver designs for LTE-Advanced networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2015

A cortical activity localization approach for decoding finger movements from human electrocorticogram signal.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

Intra-body communication model based on variable biological parameters.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015

2014
Link adaptation for wireless systems.
Wireless Communications and Mobile Computing, 2014

High SNR Linear Estimation of Vector Sources.
IEEE Wireless Commun. Letters, 2014

Decentralized Estimation Under Correlated Noise.
IEEE Trans. Signal Processing, 2014

Multicopy Cache: A Highly Energy-Efficient Cache Architecture.
ACM Trans. Embedded Comput. Syst., 2014

Algorithms and Architectures of Energy-Efficient Error-Resilient MIMO Detectors for Memory-Dominated Wireless Communication Systems.
IEEE Trans. on Circuits and Systems, 2014

Joint Power Management and Adaptive Modulation and Coding for Wireless Communications Systems With Unreliable Buffering Memories.
IEEE Trans. on Circuits and Systems, 2014

Equi-Noise: A Statistical Model That Combines Embedded Memory Failures and Channel Noise.
IEEE Trans. on Circuits and Systems, 2014

Full-Duplex Systems Using Multi-Reconfigurable Antennas.
CoRR, 2014

On optimizing the performance of interference-limited cellular systems.
Proceedings of the 2014 Wireless Telecommunications Symposium, 2014

On the performance of Massive MIMO cellular systems with power amplifiers.
Proceedings of the 2014 Wireless Telecommunications Symposium, 2014

Low power reduced-complexity error-resilient MIMO detector.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

State dependent statistical timing model for voltage scaled circuits.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An interference cancellation strategy for broadcast in hierarchical cell structure.
Proceedings of the IEEE Global Communications Conference, 2014

Distributed detection for wireless sensor networks with fusion center under correlated noise.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014

2013
A Note on "Amplify-and-Forward Relay Networks under Received Power Constraint".
IEEE Trans. Wireless Communications, 2013

Rate Gain Region and Design Tradeoffs for Full-Duplex Wireless Communications.
IEEE Trans. Wireless Communications, 2013

A survey of cross-layer power-reliability tradeoffs in multi and many core systems-on-chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

Balancing Spectral Efficiency, Energy Consumption, and Fairness in Future Heterogeneous Wireless Systems with Reconfigurable Devices.
IEEE Journal on Selected Areas in Communications, 2013

Self-interference cancellation with phase noise induced ICI suppression for full-duplex systems.
Proceedings of the 2013 IEEE Global Communications Conference, 2013

Low overhead correction scheme for unreliable LDPC buffering.
Proceedings of the IEEE Global Conference on Signal and Information Processing, 2013

Heterogeneous memory management for 3D-DRAM and external DRAM with QoS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Error-aware power management for memory dominated OFDM systems.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

MPMAP : A high level synthesis and mapping tool for MPSoCs.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

Self-interference cancellation with nonlinear distortion suppression for full-duplex systems.
Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012
Linear Estimation of Correlated Vector Sources for Wireless Sensor Networks with Fusion Center.
IEEE Wireless Commun. Letters, 2012

A Best-First Soft/Hard Decision Tree Searching MIMO Decoder for a 4 × 4 64-QAM System.
IEEE Trans. VLSI Syst., 2012

Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling.
IEEE Trans. VLSI Syst., 2012

Linear Decentralized Estimation of Correlated Data for Power-Constrained Wireless Sensor Networks.
IEEE Trans. Signal Processing, 2012

Error-Aware Algorithm/Architecture Coexploration for Video Over Wireless Applications.
ACM Trans. Embedded Comput. Syst., 2012

Joint Detection and Decoding for MIMO Systems Using Convolutional Codes: Algorithm and VLSI Architecture.
IEEE Trans. on Circuits and Systems, 2012

Optimized scheduling algorithm for LTE downlink system.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Multiuser communications using beam-tilting antennas.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

Spectral efficiency and energy consumption tradeoffs for reconfigurable devices in heterogeneous wireless systems.
Proceedings of the 2012 IEEE Wireless Communications and Networking Conference, 2012

History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Fast error aware model for arithmetic and logic circuits.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Error resilient MIMO detector for memory-dominated wireless communication systems.
Proceedings of the 2012 IEEE Global Communications Conference, 2012

Reliable low power Distributed Arithmetic filters via N-Modular Redundancy.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Session MA6b: DSP Architecture for wireless communications (invited).
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011
Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation.
IEEE Trans. VLSI Syst., 2011

Embedded Memories Fault-Tolerant Pre- and Post-Silicon Optimization.
IEEE Trans. VLSI Syst., 2011

Linear decentralized estimation of correlated data for wireless sensor networks.
Proceedings of the 8th Annual IEEE Communications Society Conference on Sensor, 2011

Reconfigurable filter implementation of a matched-filter based spectrum sensor for Cognitive Radio systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Adjustable supply voltages and refresh cycle for process variations, temperature changes, and device degradation adaptation in 1T1C embedded DRAM.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Area, reconfiguration delay and reliability trade-offs in designing reliable multi-mode FIR filters.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Energy aware task mapping algorithm for heterogeneous MPSoC based architectures.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

Using Reconfigurable Devices to Maximize Spectral Efficiency in Future Heterogeneous Wireless Systems.
Proceedings of 20th International Conference on Computer Communications and Networks, 2011

Multiuser Sum MSE Minimization Relaying Strategy.
Proceedings of IEEE International Conference on Communications, 2011

Amplify-and-Forward Relay Networks under Received Power Constraint with Imperfect CSI.
Proceedings of IEEE International Conference on Communications, 2011

A Class of Low Power Error Compensation Iterative Decoders.
Proceedings of the Global Communications Conference, 2011

Reliability-aware placement in SRAM-based FPGA for voltage scaling realization in the presence of process variations.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010
Reduced Overhead Training for Multi Reconfigurable Antennas with Beam-Tilting Capability.
IEEE Trans. Wireless Communications, 2010

Design and Implementation of a Sort-Free K-Best Sphere Decoder.
IEEE Trans. VLSI Syst., 2010

Low-Power Multimedia System Design by Aggressive Voltage Scaling.
IEEE Trans. VLSI Syst., 2010

A Radius Adaptive K-Best Decoder With Early Termination: Algorithm and VLSI Architecture.
IEEE Trans. on Circuits and Systems, 2010

Evaluation Framework for k-Best Sphere Decoders.
Journal of Circuits, Systems, and Computers, 2010

A best-first tree-searching approach for ML decoding in MIMO system.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Effect of body biasing on embedded SRAM failure.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Placement-aware partial reconfiguration for a class of FIR-like structures.
Proceedings of the 17th International Conference on Telecommunications, 2010

A Unified Hardware and Channel Noise Model for Communication Systems.
Proceedings of the Global Communications Conference, 2010

Exploiting Architectural Similarities and Mode Sequencing in Joint Cost Optimization of Multi-mode FIR Filters.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Process variation aware transcoding for low power H.264 decoding.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

E < MC2: less energy through multi-copy cache.
Proceedings of the 2010 International Conference on Compilers, 2010

2009
Amplify-and-Forward Relay Networks Under Received Power Constraint.
IEEE Trans. Wireless Communications, 2009

Architectural Optimizations for Low-Power -Best MIMO Decoders.
IEEE Trans. Vehicular Technology, 2009

Design and Implementation of a Scalable Channel Emulator for Wideband MIMO Systems.
IEEE Trans. Vehicular Technology, 2009

A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment.
IEEE Trans. VLSI Syst., 2009

Demonstration of highly programmable downlink OFDMA (WiMax) transceivers for SDR systems.
Proceedings of the 10th ACM Interational Symposium on Mobile Ad Hoc Networking and Computing, 2009

Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems.
Proceedings of the FCCM 2009, 2009

Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling.
Proceedings of the Design, Automation and Test in Europe, 2009

TRAM: A tool for Temperature and Reliability Aware Memory Design.
Proceedings of the Design, Automation and Test in Europe, 2009

A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache).
Proceedings of the 2009 International Conference on Compilers, 2009

2008
Optimizations of a MIMO Relay Network.
IEEE Trans. Signal Processing, 2008

Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

Joint Power Loading of Data and Pilots in OFDM Using Imperfect Channel State Information at the Transmitter.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

On Channel Estimation and Capacity for Amplify and Forward Relay Networks.
Proceedings of the Global Communications Conference, 2008. GLOBECOM 2008, New Orleans, LA, USA, 30 November, 2008

Cross-layer co-exploration of exploiting error resilience for video over wireless applications.
Proceedings of the 6th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia, 2008

A partial memory protection scheme for higher effective yield of embedded memory for video data.
Proceedings of the 13th Asia-Pacific Computer Systems Architecture Conference, 2008

2007
Simulation, implementation and performance evaluation of a diversity enabled WCDMA mobile terminal.
Wireless Personal Communications, 2007

Design and Implementation of a Baseband WCDMA Dual-Antenna Mobile Terminal.
IEEE Trans. on Circuits and Systems, 2007

Fault Tolerant Approaches Targeting Ultra Low Power Communications System Design.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

Cross Layer Error Exploitation for Aggressive Voltage Scaling.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Limits on voltage scaling for caches utilizing fault tolerant techniques.
Proceedings of the 25th International Conference on Computer Design, 2007

A Scalable Wireless Channel Emulator for Broadband MIMO Systems.
Proceedings of IEEE International Conference on Communications, 2007

Power Management for Cognitive Radio Platforms.
Proceedings of the Global Communications Conference, 2007

On Signal Processing Methods for MIMO Relay Architectures.
Proceedings of the Global Communications Conference, 2007

Error-Aware Design.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

An Alternative Organization of Defect Map for Defect-Resilient Embedded On-Chip Memories.
Proceedings of the Advances in Computer Systems Architecture, 2007

2006
Implementation of a carrier frequency recovery loop for MIMO-CDMA systems.
Proceedings of the IEEE Wireless Communications and Networking Conference, 2006

A Real-Time Wireless Channel Emulator for MIMO Systems.
Proceedings of the 64th IEEE Vehicular Technology Conference, 2006

System-Level SRAM Yield Enhancement.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Design and Analysis of Low Power Image Filters Toward Defect-Resilient Embedded Memories for Multimedia SoCs.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Design and VLSI implementation for a WCDMA multipath searcher.
IEEE Trans. Vehicular Technology, 2005

Wireless field trial results of a high hopping rate FHSS-FSK testbed.
IEEE Journal on Selected Areas in Communications, 2005

Improving effective yield through error tolerant system design.
Proceedings of the 12th IEEE International Conference on Electronics, 2005

A low-power ASIC implementation of 2Mbps antenna-rake combiner for WCDMA with MRC and LMS capabilities.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

Implementation of a digital timing recovery circuit for CDMA applications.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
Modified all digital timing tracking loop for wireless applications.
Proceedings of IEEE International Conference on Communications, 2003

2002
Interpolation based direct digital frequency synthesis for wireless communications.
Proceedings of the 2002 IEEE Wireless Communications and Networking Conference Record, 2002


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