Muhammad Nummer

According to our database, Muhammad Nummer authored at least 8 papers between 2001 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

A 224 Gb/s 3 pJ/bit 40 dB Insertion Loss Transceiver in 3-nm FinFET CMOS.

Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw C. H. Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin

IEEE J. Solid State Circuits, January, 2025

A 224Gb/s 3pJ/bit 42dB Insertion Loss Post-FEC Error Free Transceiver in 3-nm FinFET CMOS (Invited).

Dirk Pfaff, Muhammad Nummer, Noman Hai, Jingjing Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Choon-Haw CH Leong, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Tahseen Shakir, Carlos Carvalho, Howard Huang, Ralph Mason, Fahmida Brishty, Ifrah Jaffri, David A. Yokoyama-Martin

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS.

Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson R. Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2011

Experimental Results for Slow-speed Timing Characterization of High-speed Pipelined Datapaths.

Muhammad Nummer, Manoj Sachdev

J. Electron. Test., 2011

2003

Testing high-performance pipelined circuits with slow-speed testers.

Muhammad Nummer, Manoj Sachdev

ACM Trans. Design Autom. Electr. Syst., 2003

A DFT Technique for Testing High-Speed Circuits with Arbitrarily Slow Testers.

Muhammad Nummer, Manoj Sachdev

J. Electron. Test., 2003

DFT for Testing igh-Performance Pipelined Circuits with Slow-Speed Testers.

Muhammad Nummer, Manoj Sachdev

Proceedings of the 2003 Design, 2003

2001

A Methodology for Testing High-Performance Circuits at Arbitrarily Low Test Frequency.

Muhammad Nummer, Manoj Sachdev

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001