According to our database1, Dirk Pfaff authored at least 4 papers between 2008 and 2020.
Legend:Book In proceedings Article PhD thesis Other
A 14-GHz Bang-Bang Digital PLL With Sub-150-fs Integrated Jitter for Wireline Applications in 7-nm FinFET CMOS.
IEEE J. Solid State Circuits, 2020
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
A 14-GHz Bang-Bang Digital PLL with sub-150fs Integrated Jitter for Wireline Applications in 7nm FinFET.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
A 1.8W 115Gb/s Serial Link for Fully Buffered DIMM with 2.1ns Pass-Through Latency in 90nm CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008