Tom Eeckelaert

According to our database, Tom Eeckelaert authored at least 9 papers between 2003 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

7.3 A 224Gb/s 3pJ/b 40dB Insertion Loss Transceiver in 3nm FinFET CMOS.

Dirk Pfaff, Muhammad Nummer, Noman Hai, Peter Xia, Kai Ge Yang, Mohammad-Mahdi Mohsenpour, Marc-Andre LaCroix, Babak Zamanlooy, Tom Eeckelaert, Dmitry Petrov, Mostafa Haroun, Carson Dick, Alif Zaman, Haitao Mei, Shahab Moazzeni, Tahseen Shakir, Carlos Carvalho, Howard Huang, Pratibha Kumari, Ralph Mason, Fahmida Brishty, Ifrah Jaffri

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2007

Automated synthesis of complex analog circuits.

Georges G. E. Gielen, Tom Eeckelaert, Ewout Martens, Trent McConaghy

Proceedings of the 18th European Conference on Circuit Theory and Design, 2007

An efficient methodology for hierarchical synthesis of mixed-signal systems with fully integrated building block topology selection.

Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

A Continuous-Time Delta-Sigma Modulator for 802.11a/b/g WLAN Implemented with a Hierarchical Bottom-up Optimization Methodology.

Raf Schoofs, Tom Eeckelaert, Michiel Steyaert, Georges G. E. Gielen, Willy M. C. Sansen

Proceedings of the 13th IEEE International Conference on Electronics, 2006

Hierarchical bottom--up analog optimization methodology validated by a delta-sigma A/D converter design for the 802.11a/b/g standard.

Tom Eeckelaert, Raf Schoofs, Georges G. E. Gielen, Michiel Steyaert, Willy M. C. Sansen

Proceedings of the 43rd Design Automation Conference, 2006

2005

CAFFEINE: Template-Free Symbolic Model Generation of Analog Circuits via Canonical Form Functions and Genetic Programming.

Trent McConaghy, Tom Eeckelaert, Georges G. E. Gielen

Proceedings of the 2005 Design, 2005

Efficient Multiobjective Synthesis of Analog Circuits using Hierarchical Pareto-Optimal Performance Hypersurfaces.

Tom Eeckelaert, Trent McConaghy, Georges G. E. Gielen

Proceedings of the 2005 Design, 2005

Performance space modeling for hierarchical synthesis of analog integrated circuits.

Georges G. E. Gielen, Trent McConaghy, Tom Eeckelaert

Proceedings of the 42nd Design Automation Conference, 2005

2003

Generalized Posynomial Performance Modeling.

Tom Eeckelaert, Walter Daems, Georges G. E. Gielen, Willy M. C. Sansen

Proceedings of the 2003 Design, 2003