Myeong-Hoon Oh

According to our database1, Myeong-Hoon Oh authored at least 14 papers between 2004 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2021
PCIe Bridge Hardware for Gen-Z Memory System.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

Verification of Interconnect RTL Code for Memory-Centric Computing using UVM.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

Performance Evaluation of Fabric-Attached Memory Pool for AI Applications.
Proceedings of the International Conference on Electronics, Information, and Communication, 2021

2020
Persistent Memory Object Storage and Indexing for Scientific Computing.
Proceedings of the IEEE/ACM Workshop on Memory Centric High Performance Computing, 2020

2017
Design of a clockless MSP430 core using mixed asynchronous design flow.
IEICE Electron. Express, 2017

2014
Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC.
IEICE Trans. Electron., 2014

2011
472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device.
IEICE Electron. Express, 2011

Fine-grained power gating of datapath using FSM.
Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Design of asynchronous 2-phase ternary encoding protocol using multiple-valued logic.
Proceedings of the International SoC Design Conference, 2011

2010
Functional unit duplication for reducing dynamic power.
IEICE Electron. Express, 2010

2008
Low Static Powered Asynchronous Data Transfer for GALS System.
IEICE Trans. Inf. Syst., 2008

2007
Asynchronous Functional Coupling for Low Power Sensor Network Processors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

2005
Low Delay-Power Product Current-Mode Multiple Valued Logic for Delay-Insensitive Data Transfer Mechanism.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

2004
A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic.
Proceedings of the Integrated Circuit and System Design, 2004


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