Jeong-Gun Lee

Dongyoung Kim

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

Improved Generalization from Limiting Attention in a Transformer for Sleep Stage Classification.

[BibT_eX]

[DOI]

Dongyoung Kim

Dong-Kyu Kim

Proceedings of the International Conference on Electronics, Information, and Communication, 2024

2023

Automatic Sleep Stage Classification Using Deep Learning Algorithm for Multi-Institutional Database.

[BibT_eX]

[DOI]

IEEE Access, 2023

2022

Entropy-Based Model Generalization for Sleep Stage Classification.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Information and Communication Technology Convergence, 2022

2021

Filter combination learning for CNN model compression.

[BibT_eX]

[DOI]

Jaemin Jeong

Ji-Ho Cho

ICT Express, 2021

Image-based Sleep Stage Classification Model for Multi-Institutional Dataset.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Information and Communication Technology Convergence, 2021

Sleep Stage Classification for Inter-institutional Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Information and Communication Technology Convergence, 2021

2020

In-Situ Timing Error Predictor-Based Two-Cycle Adaptive Frequency Scaling System on an FPGA.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2020

FPGA-Based Multi-Level Approximate Multipliers for High-Performance Error-Resilient Applications.

[BibT_eX]

[DOI]

IEEE Access, 2020

Zero-Keep Filter Pruning for Energy Efficient Deep Neural Network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Information and Communication Technology Convergence, 2020

Filter Combination Learning for Convolutional Neural Network.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Information and Communication Technology Convergence, 2020

2019

G-DCF: Improving System Spectral Efficiency through Concurrent Transmissions in Wireless LANs.

[BibT_eX]

[DOI]

Wirel. Commun. Mob. Comput., 2019

A Carry Chain-Based ADMFC Design on an FPGA for EMI Reduction and Noise Compensation.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

A GALS design based on multi-frequency clocking for digital switching noise reduction.

[BibT_eX]

[DOI]

Integr., 2019

A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2019

Energy-Area-Efficient Approximate Multipliers for Error-Tolerant Applications on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

2018

Analysis of Clock Scheduling in Frequency Domain for Digital Switching Noise Suppressions.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Measurements of metastability in MUTEX on an FPGA.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2018

A GALS Design with Opposite-Phase Local Clock Assignment for Power Supply Noise Reduction.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Asia Pacific Conference on Circuits and Systems, 2018

2017

Design of a clockless MSP430 core using mixed asynchronous design flow.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2017

A performance, power, and energy analysis of ultrasound B-mode imaging on a GPU with VFS.

[BibT_eX]

[DOI]

Thi Yen Phuong

Deok-Young Lee

Concurr. Comput. Pract. Exp., 2017

Energy-efficient and high performance 2-phase asynchronous micropipelines.

[BibT_eX]

[DOI]

Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Exploring the current consumption of an Intel Edison module for IoT applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2017

2016

A performance-aware yield analysis and optimization of manycore architectures.

[BibT_eX]

[DOI]

Sanghoon Kwak

Comput. Electr. Eng., 2016

2015

Design space exploration of SW beamformer on GPU.

[BibT_eX]

[DOI]

Thi Yen Phuong

Concurr. Comput. Pract. Exp., 2015

2014

Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC.

[BibT_eX]

[DOI]

Myeong-Hoon Oh

IEICE Trans. Electron., 2014

A Low EMI Circuit Design with Asynchronous Multi-Frequency Clocking.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2014

Deduplication TAR Scheme Using User-Level File System.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2014

Software based ultrasound B-mode/beamforming optimization on GPU and its performance prediction.

[BibT_eX]

[DOI]

Thi Yen Phuong

Proceedings of the 21st International Conference on High Performance Computing, 2014

2012

Triggering navigators for innovative system design: The case of lab-on-a-chip technology.

[BibT_eX]

[DOI]

Expert Syst. Appl., 2012

Asynchronous Circuit Design on an FPGA: MIPS Processor Case Study.

[BibT_eX]

[DOI]

Proceedings of the Convergence and Hybrid Information Technology, 2012

Low Latency Scheduling on Multi BOOST Environment.

[BibT_eX]

[DOI]

Proceedings of the Convergence and Hybrid Information Technology, 2012

2011

472MHz throughput asynchronous FIFO design on a Virtex-5 FPGA device.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2011

Low area and high speed SHA-1 implementation.

[BibT_eX]

[DOI]

Eun-Gu Jung

Daewan Han

Proceedings of the International SoC Design Conference, 2011

Monitoring and Feedback Tools for Realtime Workloads for Xen Virtual Machine.

[BibT_eX]

[DOI]

Proceedings of the International Conference on IT Convergence and Security, 2011

Energy Efficient File Transfer Mechanism Using Deduplication Scheme.

[BibT_eX]

[DOI]

Proceedings of the Convergence and Hybrid Information Technology, 2011

Minimizing Scheduling Delay for Multimedia in Xen Hypervisor.

[BibT_eX]

[DOI]

Kyung Woo Hur

Young Woong Ko

Proceedings of the Advanced Communication and Networking, 2011

Data Deduplication System for Supporting Multi-mode.

[BibT_eX]

[DOI]

Proceedings of the Intelligent Information and Database Systems, 2011

2010

A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

Exploration of Power-Delay Trade-Offs with Heterogeneous Adders by Integer Linear Programming.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2009

Intelligent sensor node based a low power ECG monitoring system.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2009

An Asymptotic Performance/Energy Analysis and Optimization of Multi-core Architectures.

[BibT_eX]

[DOI]

Eun-Gu Jung

Wook Shin

Proceedings of the Distributed Computing and Networking, 10th International Conference, 2009

2008

Embedding High-Performance Synchronous Routers to Asynchronous Network on Chip.

[BibT_eX]

Eun-Gu Jung

Proceedings of the 2008 International Conference on Computer Design, 2008

2007

Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 2007

Implications of Rent's Rule for NoC Design and Its Fault-Tolerance.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

A Design Method for Heterogeneous Adders.

[BibT_eX]

[DOI]

Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

2005

Instruction level redundant number computations for fast data intensive processing in asynchronous processors.

[BibT_eX]

[DOI]

J. Syst. Archit., 2005

Procedural Constraints in the Extended RBAC and the Coloured Petri Net Modeling.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Design of a Mutated Adder and Its Optimization Using ILP Formulation.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

A Low Latency Asynchronous FIFO Combining a Wave Pipeline with a Handshake Scheme.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Low Latency Four-Flop Synchronizer with the Handshake Interface.

[BibT_eX]

[DOI]

Suk-Jin Kim

Kiseon Kim

IEICE Trans. Inf. Syst., 2005

Asynchronous Multiple-Issue On-Chip Bus with In-Order/Out-of-Order Completion.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2005

Differential Value Encoding for Delay Insensitive Handshake Protocol.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2005

High performance asynchronous on-chip bus with multiple issue and out-of-order/in-order completion.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Efficient Buffer Allocation for Asynchronous Linear Pipelines by Design Space Localization.

[BibT_eX]

[DOI]

Proceedings of the Advances in Computer Systems Architecture, 9th Asia-Pacific Conference, 2004

2003

Distributed Synchronous Control Units for Dataflow Graphs under Allocation of Telescopic Arithmetic Units.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Performance optimization of synchronous control units for datapaths with variable delay arithmetic units.

[BibT_eX]

[DOI]

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2001

Imprecise data computation for high performance asynchronous processors.

[BibT_eX]

[DOI]

Proceedings of ASP-DAC 2001, 2001

Building a Distributed Asynchronous Control Unit through Automatic Derivation of Hierarchically Decomposed AFSMs from a CDFG.

[BibT_eX]

[DOI]

Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001

2000

Automatic distributed asynchronous control circuit generation from data flow graph for asynchronous high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Automatic Process-Oriented Control Circuit Generation for Asynchronous High-Level Synthesis.

[BibT_eX]

[DOI]