Delong Shang

Orcid: 0009-0000-6674-2347

According to our database1, Delong Shang authored at least 54 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems.
IEEE Access, 2024

2023
An exponential function accelerator with radix-16 algorithm for spiking neural networks.
IEICE Electron. Express, 2023

Blended Glial Cell's Spiking Neural Network.
IEEE Access, 2023

HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method.
IEEE Access, 2023

ORSAS: An Output Row-Stationary Accelerator for Sparse Neural Networks.
IEEE Access, 2023

AMA-Det: Enhancing Shared Head of One-Stage Object Detection With Adaptation, Merging, and Alignment.
IEEE Access, 2023

2022
Design of low latency asynchronous arbiter based on standard cell library.
IEICE Electron. Express, 2022

2021
Gradient Corrected Approximation for Binary Neural Networks.
IEICE Trans. Inf. Syst., 2021

Face Template Protection through Residual Learning Based Error-Correcting Codes.
Proceedings of the ICCCV 2021: 4th International Conference on Control and Computer Vision, Macau, SAR, China, August 13, 2021

2018
Modelling Switched-Capacitor DC-DC Converters with Signal Transition Graphs.
Proceedings of the 15th International Conference on Synthesis, 2018

Approximate Fixed-Point Elementary Function Accelerator for the SpiNNaker-2 Neuromorphic Chip.
Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2016
Design of a DCO based on worst-case delay of a self-timed counter and a digitally controllable delay path.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

A smart all-digital charge to digital converter.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Low power voltage sensing through capacitance to digital conversion.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Fast capacitance-to-digital converter with internal reference.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2016

2015
Wideband dynamic voltage sensing mechanism for EH systems.
Proceedings of the 25th International Workshop on Power and Timing Modeling, 2015

An elastic timer for wide dynamic working range.
Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

2014
Asynchronously assisted FPGA for variability.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Asynchronous design for new on-chip wide dynamic range power electronics.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Concurrent Multiresource Arbiter: Design and Applications.
IEEE Trans. Computers, 2013

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2013

Variability analysis of self-timed SRAM robustness.
Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

Wide-range, reference free, on-chip voltage sensor for variable Vdd operations.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High-order reconfigurable FIR filter design based on statistical analysis of CSD coefficients.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

2012
Towards power-elastic systems through concurrency management.
IET Comput. Digit. Tech., 2012

A hybrid power delivery method for asynchronous loads in energy harvesting systems.
Proceedings of the 10th IEEE International NEWCAS Conference, 2012

Ultra-low power transmitter.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Self-Timed SRAM for Energy Harvesting Systems.
J. Low Power Electron., 2011

A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems.
ACM J. Emerg. Technol. Comput. Syst., 2011

Improving the Robustness of Self-timed SRAM to Variable Vdds.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Variation tolerant asynchronous FPGA (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Variation Tolerant AFPGA Architecture.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

2010
Highly parallel multi-resource arbiters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Asynchronous FPGA architecture with distributed control.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Stochastic analysis of power, latency and the degree of concurrency.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Fine-grain stochastic modelling of dynamic power management policies and analysis of their power - latency tradeoffs.
IET Softw., 2009

The Magic Rule of Tiles: Virtual Delay Insensitivity.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

Modular Approach to Multi-resource Arbiter Design.
Proceedings of the 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009

2008
Phase-Encoding for On-Chip Signalling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

2007
Registers for Phase Difference Based Logic.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Dynamic global security-aware synthesis using SystemC.
IET Comput. Digit. Tech., 2007

Asynchronous Functional Coupling for Low Power Sensor Network Processors.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007

The Design of Virtual Self-timed Block for Activity Communication in SOC.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006
Low-Cost Online Testing of Asynchronous Handshakes.
Proceedings of the 11th European Test Symposium, 2006

Multiple-Rail Phase-Encoding for NoC.
Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC 2006), 2006

2005
PSK Signalling on NoC Buses.
Proceedings of the Integrated Circuit and System Design, 2005

On-Line Testing of Globally Asynchronous Circuits.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

2004
A Low and Balanced Power Implementation of the AES Security Mechanism Using Self-Timed Circuits.
Proceedings of the Integrated Circuit and System Design, 2004

An Asynchronous Synthesis Toolset Using Verilog.
Proceedings of the 2004 Design, 2004

2002
Data Communication in Systems with Heterogeneous Timing.
IEEE Micro, 2002

Asynchronous circuit synthesis via direct translation.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
Synthesis and Implementation of a Signal-Type Asynchronous Data Communication Mechanism.
Proceedings of the 7th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2001), 2001

2000
Asynchronous Communication Mechanisms Using Self-Timed Circuits.
Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000


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