Myong Hyon Cho

According to our database1, Myong Hyon Cho authored at least 13 papers between 2008 and 2013.

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Bibliography

2013
On-chip networks for manycore architecture.
PhD thesis, 2013

Optimal and Heuristic Application-Aware Oblivious Routing.
IEEE Trans. Computers, 2013

Design tradeoffs for simplicity and efficient verification in the Execution Migration Machine.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
HORNET: A Cycle-Level Multicore Simulator.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

2011
Brief announcement: distributed shared memory based on computation migration.
Proceedings of the SPAA 2011: Proceedings of the 23rd Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2011

Deadlock-free fine-grained thread migration.
Proceedings of the NOCS 2011, 2011

Scalable, accurate multicore simulation in the 1000-core era.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2011

Memory coherence in the age of multicores.
Proceedings of the IEEE 29th International Conference on Computer Design, 2011

2009
Static virtual channel allocation in oblivious routing.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Path-based, randomized, oblivious, minimal routing.
Proceedings of the Second International Workshop on Network on Chip Architectures, 2009

Application-aware deadlock-free oblivious routing.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Oblivious Routing in On-Chip Bandwidth-Adaptive Networks.
Proceedings of the PACT 2009, 2009

2008
Diastolic arrays: throughput-driven reconfigurable computing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008


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