Chih-Chi Cheng

According to our database1, Chih-Chi Cheng authored at least 24 papers between 2005 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A patch memory system for image processing and computer vision.
Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2012
Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding.
IEEE J. Solid State Circuits, 2012

2011
A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009
Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.
IEEE Trans. Circuits Syst. Video Technol., 2009

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor.
IEEE J. Solid State Circuits, 2009

2008
Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.
IEEE Trans. Circuits Syst. Video Technol., 2008

iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Diastolic arrays: throughput-driven reconfigurable computing.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.
Proceedings of the 45th Design Automation Conference, 2008

2007
On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. Video Technol., 2007

124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory.
IEEE Trans. Circuits Syst. Video Technol., 2007

2006
Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling.
IEEE Trans. Signal Process., 2006

Precompression Quality-Control Algorithm for JPEG 2000.
IEEE Trans. Image Process., 2006

Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Analysis and VLSI architecture of update step in motion-compensated temporal filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Frame-level data reuse for motion-compensated temporal filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.
Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Line Buffer Wordlength Analysis for Line-Based 2-D DWT.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005
Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.
Proceedings of the Seventh IEEE International Symposium on Multimedia (ISM 2005), 2005

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Memory efficient JPEG2000 architecture with stripe pipeline scheme.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005


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