Chih-Chi Cheng

According to our database¹, Chih-Chi Cheng authored at least 24 papers between 2005 and 2016.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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Article

PhD thesis

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On csauthors.net:

Bibliography

2016

A patch memory system for image processing and computer vision.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual IEEE/ACM International Symposium on Microarchitecture, 2016

2012

Quad Full-HD Transform Engine for Dual-Standard Low-Power Video Coding.

[BibT_eX]

[DOI]

Rahul Rithe

Chih-Chi Cheng

Anantha P. Chandrakasan

IEEE J. Solid State Circuits, 2012

2011

A 216fps 4096×2160p 3DTV set-top box SoC for free-viewpoint 3DTV applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010

A 0.077 to 0.168 nJ/bit/iteration scalable 3GPP LTE turbo decoder with an adaptive sub-block parallel scheme and an embedded DVFS engine.

[BibT_eX]

[DOI]

Chih-Chi Cheng

Yi-Min Tsai

Liang-Gee Chen

Anantha P. Chandrakasan

Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

2009

Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System.

[BibT_eX]

[DOI]

Chih-Chi Cheng

Po-Chih Tseng

Liang-Gee Chen

IEEE Trans. Circuits Syst. Video Technol., 2009

iVisual: An Intelligent Visual Sensor SoC With 2790 fps CMOS Image Sensor and 205 GOPS/W Vision Processor.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

2008

Efficient Architecture Design of Motion-Compensated Temporal Filtering/Motion Compensated Prediction Engine.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2008

iVisual: An Intelligent Visual Sensor SoC with 2790fps CMOS Image Sensor and 205GOPS/W Vision Processor.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Diastolic arrays: throughput-driven reconfigurable computing.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

On-Chip Memory Optimization Scheme for VLSI Implementation of Line-Based Two-Dimentional Discrete Wavelet Transform.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2007

124 MSamples/s Pixel-Pipelined Motion-JPEG 2000 Codec Without Tile Memory.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. Video Technol., 2007

2006

Memory Efficient JPEG 2000 Architecture With Stripe Pipeline Scheduling.

[BibT_eX]

[DOI]

IEEE Trans. Signal Process., 2006

Precompression Quality-Control Algorithm for JPEG 2000.

[BibT_eX]

[DOI]

IEEE Trans. Image Process., 2006

Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2006

A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applications.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memory.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Analysis and VLSI architecture of update step in motion-compensated temporal filtering.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Frame-level data reuse for motion-compensated temporal filtering.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Scalable Rate-Distortion-Computation Hardware Accelerator for MCTF and ME.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Multimedia and Expo, 2006

Line Buffer Wordlength Analysis for Line-Based 2-D DWT.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006

2005

Application Layer Error Correction Scheme for Video Header Protection on Wireless Network.

[BibT_eX]

[DOI]

Proceedings of the Seventh IEEE International Symposium on Multimedia (ISM 2005), 2005

Multiple-lifting scheme: memory-efficient VLSI implementation for line-based 2-D DWT.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Memory efficient JPEG2000 architecture with stripe pipeline scheme.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE International Conference on Acoustics, 2005

Chih-Chi Cheng

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