N. Nalla Anandakumar

According to our database1, N. Nalla Anandakumar authored at least 20 papers between 2012 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.
Proceedings of the IEEE European Test Symposium, 2023

Design and Analysis of FPGA-based PUFs with Enhanced Performance for Hardware-oriented Security.
ACM J. Emerg. Technol. Comput. Syst., 2022

Field Programmable Gate Array based elliptic curve Menezes-Qu-Vanstone key agreement protocol realization using Physical Unclonable Function and true random number generator primitives.
IET Circuits Devices Syst., 2022

PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs.
IACR Cryptol. ePrint Arch., 2022

Implementation of Efficient XOR Arbiter PUF on FPGA With Enhanced Uniqueness and Security.
IEEE Access, 2022

FPGA-based Physical Unclonable Functions: A comprehensive overview of theory and architectures.
Integr., 2021

FPGA Implementations of Espresso Stream Cipher.
Proceedings of the 28th IEEE International Conference on Electronics, 2021

FPGA-Based True Random Number Generation Using Programmable Delays in Oscillator-Rings.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

Efficient and Lightweight FPGA-based Hybrid PUFs with Improved Performance.
Microprocess. Microsystems, 2020

Design, Implementation and Analysis of Efficient Hardware-Based Security Primitives.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

A Survey of Security Attacks on Silicon Based Weak PUF Architectures.
Proceedings of the Security in Computing and Communications - 8th International Symposium, 2020

Modeling Attacks and Efficient Countermeasures on Interpose PUF.
Proceedings of the Foundations and Practice of Security - 13th International Symposium, 2020

Reconfigurable Hardware Architecture for Authenticated Key Agreement Protocol Over Binary Edwards Curve.
ACM Trans. Reconfigurable Technol. Syst., 2018

Key Retrieval from AES Architecture Through Hardware Trojan Horse.
Proceedings of the Security in Computing and Communications - 6th International Symposium, 2018

Compact Implementations of FPGA-based PUFs with Enhanced Performance.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

SCA Resistance Analysis of MAC-PHOTON.
IACR Cryptol. ePrint Arch., 2015

SCA Resistance Analysis on FPGA Implementations of Sponge Based \mathttMAC-\mathttPHOTON.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2015

A Very Compact FPGA Implementation of LED and PHOTON.
IACR Cryptol. ePrint Arch., 2014

Correlation power analysis attack of AES on FPGA using customized communication protocol.
Proceedings of the Second International Conference on Computational Science, 2012