Jungmin Park

According to our database1, Jungmin Park authored at least 26 papers between 2011 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.



In proceedings 
PhD thesis 


On csauthors.net:


Power Side-Channel Leakage Assessment Framework at Register-Transfer Level.
IEEE Trans. Very Large Scale Integr. Syst., 2022

RASCv2: Enabling Remote Access to Side-Channels for Mission Critical and IoT Systems.
ACM Trans. Design Autom. Electr. Syst., 2022

PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022

Secure Physical Design.
IACR Cryptol. ePrint Arch., 2022

Real-time instruction-level verification of remote IoT/CPS devices via side channels.
Discov. Internet Things, 2022

LDTFI: Layout-aware Timing Fault-Injection Attack Assessment Against Differential Fault Analysis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

PSC-TG: RTL Power Side-Channel Leakage Assessment with Test Pattern Generation.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

QEC: A Quantum Entropy Chip and Its Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2020

SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.
ACM Trans. Design Autom. Electr. Syst., 2020

Adaptive Attitude Estimation for Low-Cost MEMS IMU Using Ellipsoidal Method.
IEEE Trans. Instrum. Meas., 2020

Parameter Estimation of Radar Noise Model for Terrain Referenced Navigation Using a New EM Initialization Method.
IEEE Trans. Aerosp. Electron. Syst., 2020

Extraction and prioritization of product attributes using an explainable neural network.
Pattern Anal. Appl., 2020

Leveraging Side-Channel Information for Disassembly and Security.
ACM J. Emerg. Technol. Comput. Syst., 2020

RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

SCR-QRNG: Side-Channel Resistant Design using Quantum Random Number Generator.
Proceedings of the International Conference on Computer-Aided Design, 2019

Robust Timing Attack Countermeasure on Virtual Hardware.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Hardware virtualization for protection against power analysis attack.
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018

Power-based side-channel instruction-level disassembler.
Proceedings of the 55th Annual Design Automation Conference, 2018

Using Power Clues to Hack IoT Devices: The power side channel provides for instruction-level disassembly.
IEEE Consumer Electron. Mag., 2017

ATAVE: A framework for automatic timing attack vulnerability evaluation.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017

Security Metrics for Power Based SCA Resistant Hardware Implementation.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

t-Private Systems: Unified Private Memories and Computation.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2014

Towards Making Private Circuits Practical: DPA Resistant Private Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

t-Private logic synthesis on FPGAs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Approach to Generating Monitoring Code toward Advanced Self-healing.
Proceedings of the Control and Automation, and Energy System Engineering, 2011