Kimia Zamiri Azar

Orcid: 0000-0001-5684-100X

According to our database1, Kimia Zamiri Azar authored at least 30 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2024
SiPGuard: Run-Time System-in-Package Security Monitoring via Power Noise Variation.
IEEE Trans. Very Large Scale Integr. Syst., February, 2024

Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Improving Bounded Model Checkers Scalability for Circuit De-Obfuscation: An Exploration.
IEEE Trans. Inf. Forensics Secur., 2024

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.
IEEE Access, 2024

2023
TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Metrics-to-Methods: Decisive Reverse Engineering Metrics for Resilient Logic Locking.
Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.
Proceedings of the IEEE European Test Symposium, 2023

QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

EnSAFe: Enabling Sustainable SoC Security Auditing using eFPGA-based Accelerators.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

SheLL: Shrinking eFPGA Fabrics for Logic Locking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SHarPen: SoC Security Verification by Hardware Penetration Test.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
Advances in Logic Locking: Past, Present, and Prospects.
IACR Cryptol. ePrint Arch., 2022

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.
IACR Cryptol. ePrint Arch., 2022

Warm Up before Circuit De-obfuscation? An Exploration through Bounded-Model-Checkers.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021
Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2021

From Cryptography to Logic Locking: A Survey on the Architecture Evolution of Secure Scan Chains.
IEEE Access, 2021

ChaoLock: Yet Another SAT-hard Logic Locking using Chaos Computing.
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

2020
ExTru: A Lightweight, Fast, and Secure Expirable Trust for the Internet of Things.
CoRR, 2020

DFSSD: Deep Faults and Shallow State Duality, A Provably Strong Obfuscation Solution for Circuits with Restricted Access to Scan Chain.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

SCRAMBLE: The State, Connectivity and Routing Augmentation Model for Building Logic Encryption.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

InterLock: An Intercorrelated Logic and Routing Locking.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex Structures.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

On Designing Secure and Robust Scan Chain for Protecting Obfuscated Logic.
Proceedings of the GLSVLSI '20: Great Lakes Symposium on VLSI 2020, 2020

2019
SMT Attack: Next Generation Attack on Obfuscated Circuits with Capabilities and Performance Beyond the SAT Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

COMA: Communication and Obfuscation Management Architecture.
Proceedings of the 22nd International Symposium on Research in Attacks, 2019

Threats on Logic Locking: A Decade Later.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing Blocks.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
DuCNoC: A High-Throughput FPGA-Based NoC Simulator Using Dual-Clock Lightweight Router Micro-Architecture.
IEEE Trans. Computers, 2018

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018


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