Fahim Rahman

Orcid: 0000-0001-9388-0112

According to our database1, Fahim Rahman authored at least 56 papers between 2015 and 2024.

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Bibliography

2024
Heterogeneous Integration Supply Chain Integrity Through Blockchain and CHSM.
ACM Trans. Design Autom. Electr. Syst., January, 2024

Advancing Trustworthiness in System-in-Package: A Novel Root-of-Trust Hardware Security Module for Heterogeneous Integration.
IEEE Access, 2024

2023
Enabling Security of Heterogeneous Integration: From Supply Chain to In-Field Operations.
IEEE Des. Test, October, 2023

FPGA-Chain: Enabling Holistic Protection of FPGA Supply Chain With Blockchain Technology.
IEEE Des. Test, April, 2023

ReTrustFSM: Toward RTL Hardware Obfuscation-A Hybrid FSM Approach.
IEEE Access, 2023

CAPEC: A Cellular Automata Guided FSM-based IP Authentication Scheme.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

TaintFuzzer: SoC Security Verification using Taint Inference-enabled Fuzzing.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

PSC-Watermark: Power Side Channel Based IP Watermarking Using Clock Gates.
Proceedings of the IEEE European Test Symposium, 2023

QuardTropy: Detecting and Quantifying Unauthorized Information Leakage in Hardware Designs using g-entropy.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

RTLock: IP Protection using Scan-Aware Logic Locking at RTL.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz Testing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP Redaction.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

SHarPen: SoC Security Verification by Hardware Penetration Test.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
eChain: A Blockchain-Enabled Ecosystem for Electronic Device Authenticity Verification.
IEEE Trans. Consumer Electron., 2022

SoFI: Security Property-Driven Vulnerability Assessments of ICs Against Fault-Injection Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ACED-IT: Assuring Confidential Electronic Design Against Insider Threats in a Zero-Trust Environment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ToSHI - Towards Secure Heterogeneous Integration: Security Risks, Threat Assessment, and Assurance.
IACR Cryptol. ePrint Arch., 2022

Digital Twin for Secure Semiconductor Lifecycle Management: Prospects and Applications.
IACR Cryptol. ePrint Arch., 2022

PQC-SEP: Power Side-channel Evaluation Platform for Post-Quantum Cryptography Algorithms.
IACR Cryptol. ePrint Arch., 2022

Secure Physical Design.
IACR Cryptol. ePrint Arch., 2022

Fuzz, Penetration, and AI Testing for SoC Security Verification: Challenges and Solutions.
IACR Cryptol. ePrint Arch., 2022

Rethinking Watermark: Providing Proof of IP Ownership in Modern SoCs.
IACR Cryptol. ePrint Arch., 2022

O'clock: lock the clock via clock-gating for SoC IP protection.
Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.
ACM Trans. Design Autom. Electr. Syst., 2021

An End-to-End Bitstream Tamper Attack Against Flip-Chip FPGAs.
IACR Cryptol. ePrint Arch., 2021

What is All the FaaS About? - Remote Exploitation of FPGA-as-a-Service Platforms.
IACR Cryptol. ePrint Arch., 2021

Quantifiable Assurance: From IPs to Platforms.
IACR Cryptol. ePrint Arch., 2021

SAIF: Automated Asset Identification for Security Verification at the Register Transfer Level.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

LL-ATPG: Logic-Locking Aware Test Using Valet Keys in an Untrusted Environment.
Proceedings of the IEEE International Test Conference, 2021

HEXON: Protecting Firmware Using Hardware-Assisted Execution-Level Obfuscation.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Prediction And Detection In Change Of Cognitive Load For VIP's By A Machine Learning Approach.
Proceedings of the 3rd IEEE International Conference on Artificial Intelligence in Engineering and Technology, 2021

AutoMap: Automated Mapping of Security Properties Between Different Levels of Abstraction in Design Flow.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

POCA: First Power-on Chip Authentication in Untrusted Foundry and Assembly.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2021

RHAT: Efficient RowHammer-Aware Test for Modern DRAM Modules.
Proceedings of the 26th IEEE European Test Symposium, 2021

BOFT: Exploitable Buffer Overflow Detection by Information Flow Tracking.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Invited: End-to-End Secure SoC Lifecycle Management.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

2020
Interconnect-Based PUF With Signature Uniqueness Enhancement.
IEEE Trans. Very Large Scale Integr. Syst., 2020

EMFORCED: EM-Based Fingerprinting Framework for Remarked and Cloned Counterfeit IC Detection Using Machine Learning Classification.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Leveraging Side-Channel Information for Disassembly and Security.
ACM J. Emerg. Technol. Comput. Syst., 2020

RanStop: A Hardware-assisted Runtime Crypto-Ransomware Detection Technique.
CoRR, 2020

SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment.
Proceedings of the 38th IEEE VLSI Test Symposium, 2020

2019
Electronics Supply Chain Integrity Enabled by Blockchain.
ACM Trans. Design Autom. Electr. Syst., 2019

Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptol. ePrint Arch., 2019

SoC Security Verification using Property Checking.
Proceedings of the IEEE International Test Conference, 2019

FPGA Bitstream Security: A Day in the Life.
Proceedings of the IEEE International Test Conference, 2019

FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019

2018
Device attestation: Past, present, and future.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
Poly-Si-Based Physical Unclonable Functions.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Beyond CMOS: Fundamentals, Applications, and Roadmap.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Introduction to Cyber-Physical System Security: A Cross-Layer Perspective.
IEEE Trans. Multi Scale Comput. Syst., 2017

iPUF: Interconnect PUF with Self-Masking Circuit for Performance Enhancement.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

Hardware-Assisted Cybersecurity for IoT Devices.
Proceedings of the 18th International Workshop on Microprocessor and SOC Test and Verification, 2017

2016
An Aging-Resistant RO-PUF for Reliable Key Generation.
IEEE Trans. Emerg. Top. Comput., 2016

Selective Enhancement of Randomness at the Materials Level: Poly-Si Based Physical Unclonable Functions (PUFs).
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

2015
Harnessing Nanoscale Device Properties for Hardware Security.
Proceedings of the 16th International Workshop on Microprocessor and SOC Test and Verification, 2015

A pair selection algorithm for robust RO-PUF against environmental variations and aging.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015


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