Nadir Achouri

According to our database1, Nadir Achouri authored at least 9 papers between 2001 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

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Bibliography

2013
Two-level compression through selective reseeding.
Proceedings of the 2013 IEEE International Test Conference, 2013

2005
Memory Defect Tolerance Architectures for Nanotechnologies.
J. Electron. Test., 2005

2004
A Diversified Memory Built-In Self-Repair Approach for Nanotechnologies.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004

2003
Memory Built-In Self-Repair for Nanotechnologies.
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Dynamic Data-bit Memory Built-In Self- Repair.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

A Memory Built-In Self-Repair for High Defect Densities Based on Error Polarities.
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

Optimal Reconfiguration Functions for Column or Data-bit Built-In Self-Repair.
Proceedings of the 2003 Design, 2003

2001
Designing and Implementing Efficient BISR Techniques for Embedded RAMs.
Proceedings of the 2nd Latin American Test Workshop, 2001


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