David Y. Lepejian

According to our database, David Y. Lepejian authored at least 5 papers between 1996 and 2001.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2001

Using Electrical Bitmap Results from Embedded Memory to Enhance Yield.

Julie Segal, Alvin Jee, David Y. Lepejian, Ben Chu

IEEE Des. Test Comput., 2001

Designing and Implementing Efficient BISR Techniques for Embedded RAMs.

Michael Nicolaidis, Slimane Boutobza, Nadir Achouri, R. D. Shawn Blanton, Julie Segal, David Y. Lepejian, Ben Chu, Tony Singh, Harvey Berman

Proceedings of the 2nd Latin American Test Workshop, 2001

2000

Tutorial Statement.

Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf

Proceedings of the 2000 Design, 2000

1998

A D&T Roundtable: Testing Mixed Logic and DRAM Chips.

Meh-Ron Amerian, William D. Atwell Jr., Ian Burgess, Gary D. Fleeman, David Y. Lepejian, T. W. Williams, Farzad Zarrinfar, Yervant Zorian

IEEE Des. Test Comput., 1998

1996

Can Defect-Tolerant Chips Better Meet the Quality Challenge?

R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996