Lorena Anghel
Orcid: 0000-0001-9569-0072Affiliations:
- Universite Grenoble Alpes, Grenoble INP, France
According to our database1,
Lorena Anghel
authored at least 123 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
-
on orcid.org
On csauthors.net:
Bibliography
2024
Enhancing Reliability of Neural Networks at the Edge: Inverted Normalization with Stochastic Affine Transformations.
CoRR, 2024
NeuSpin: Design of a Reliable Edge Neuromorphic System Based on Spintronics for Green AI.
CoRR, 2024
CoRR, 2024
2023
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023
SpinBayes: Algorithm-Hardware Co-Design for Uncertainty Estimation Using Bayesian In-Memory Approximation on Spintronic-Based Architectures.
ACM Trans. Embed. Comput. Syst., October, 2023
IEEE Trans. Emerg. Top. Comput. Intell., June, 2023
Spintronic Memristor-Based Binarized Ensemble Convolutional Neural Network Architectures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023
SpinDrop: Dropout-Based Bayesian Binary Neural Networks With Spintronic Implementation.
IEEE J. Emerg. Sel. Topics Circuits Syst., March, 2023
Scale-Dropout: Estimating Uncertainty in Deep Neural Networks Using Stochastic Scale.
CoRR, 2023
Spatial-SpinDrop: Spatial Dropout-based Binary Bayesian Neural Network with Spintronics Implementation.
CoRR, 2023
A tunable and versatile 28nm FD-SOI crossbar output circuit for low power analog SNN inference with eNVM synapses.
CoRR, 2023
Robustness and Power Efficiency in Spin-Orbit Torque-Based Probabilistic Logic Circuits.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging.
Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023
Improving the Robustness of Neural Networks to Noisy Multi-Level Non-Volatile Memory-based Synapses.
Proceedings of the International Joint Conference on Neural Networks, 2023
Leveraging Sparsity with Spiking Recurrent Neural Networks for Energy-Efficient Keyword Spotting.
Proceedings of the IEEE International Conference on Acoustics, 2023
Proceedings of the IEEE European Test Symposium, 2023
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
Design-Time Exploration for Process, Environment and Aging Compensation Techniques for Low Power Reliable-Aware Design.
IEEE Trans. Emerg. Top. Comput., 2022
A Fast, Energy Efficient and Tunable Magnetic Tunnel Junction Based Bitstream Generator for Stochastic Computing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Electrical Coupling of Perpendicular Superparamagnetic Tunnel Junctions for Probabilistic Computing.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Binary Bayesian Neural Networks for Efficient Uncertainty Estimation Leveraging Inherent Stochasticity of Spintronic Devices.
Proceedings of the 17th ACM International Symposium on Nanoscale Architectures, 2022
Spin Orbit Torque-based Crossbar Array for Error Resilient Binary Convolutional Neural Network.
Proceedings of the 23rd IEEE Latin American Test Symposium, 2022
Investigating Current-Based and Gating Approaches for Accurate and Energy-Efficient Spiking Recurrent Neural Networks.
Proceedings of the Artificial Neural Networks and Machine Learning - ICANN 2022, 2022
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022
2021
Proceedings of the IEEE International Reliability Physics Symposium, 2021
MOZART: Masking Outputs with Zeros for Architectural Robustness and Testing of DNN Accelerators.
Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021
2020
J. Electron. Test., 2020
Proceedings of the IEEE International Test Conference, 2020
A Comprehensive End-to-end Solution for a Secure and Dynamic Mixed-signal 1687 System.
Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020
2019
Proceedings of the 37th IEEE VLSI Test Symposium, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018
NBTI aged cell rejuvenation with back biasing and resulting critical path reordering for digital circuits in 28nm FDSOI.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Microprocess. Microsystems, 2017
Fully-connected single-layer STT-MTJ-based spiking neural network under process variability.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Early system failure prediction by using aging in situ monitors: Methodology of implementation and application results.
Proceedings of the 34th IEEE VLSI Test Symposium, 2016
Multi-context non-volatile content addressable memory using magnetic tunnel junctions.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016
In-situ slack monitors: taking up the challenge of on-die monitoring of variability and reliability.
Proceedings of the 1st IEEE International Verification and Security Workshop, 2016
Activity profiling: Review of different solutions to develop reliable and performant design.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016
Proceedings of the 21th IEEE European Test Symposium, 2016
Proceedings of the 2016 Euromicro Conference on Digital System Design, 2016
Workload Impact on BTI HCI Induced Aging of Digital Circuits: A System level Analysis.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Early failure prediction by using in-situ monitors: Implementation and application results.
Proceedings of the Workshop on Early Reliability Modeling for Aging and Variability in Silicon Systems, 2016
2015
IEEE Des. Test, 2015
Proceedings of the IEEE International Reliability Physics Symposium, 2015
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
2014
Fault-tolerant adaptive routing under an unconstrained set of node and link failures for many-core systems-on-chip.
Microprocess. Microsystems, 2014
Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014
Exploring the state dependent SET sensitivity of asynchronous logic - The muller-pipeline example.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014
Proceedings of the 10th European Workshop on Microelectronics Education (EWME), 2014
2013
Reliability of TSV interconnects: Electromigration, thermal cycling, and impact on above metal level dielectric.
Microelectron. Reliab., 2013
Fault-tolerant adaptive routing under permanent and temporary failures for many-core systems-on-chip.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013
2012
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems.
J. Electron. Test., 2012
Kth-Aggressor Fault (KAF)-based Thru-Silicon-Via Interconnect Built-In Self-Test and Diagnosis.
J. Electron. Test., 2012
Proceedings of the 18th IEEE International On-Line Testing Symposium, 2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
2011
Microprocess. Microsystems, 2011
Proceedings of the 12th Latin American Test Workshop, 2011
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011
Efficient Fault Detection Architecture Design of Latch-Based Low Power DSP/MCU Processor.
Proceedings of the 16th European Test Symposium, 2011
I-BIRAS: Interconnect Built-In Self-Repair and Adaptive Serialization in 3D Integrated Systems.
Proceedings of the 16th European Test Symposium, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
RILM: Reconfigurable inter-layer routing mechanism for 3D multi-layer networks-on-chip.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Interconnect Built-In Self-Repair and Adaptive-Serialization (I-BIRAS) for 3D integrated systems.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the IEEE/IFIP International Conference on Dependable Systems and Networks Workshops (DSN-W 2010), Chicago, Illinois, USA, June 28, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
An effective approach to detect logic soft errors in digital circuits based on GRAAL.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Coordinated versus Uncoordinated Checkpoint Recovery for Network-on-Chip Based Systems.
Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008
2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.
J. Electron. Test., 2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the Computational and Ambient Intelligence, 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007
2006
Multiple Defect Tolerant Devices for Unreliable Future Nanotechnologies.
Proceedings of the 7th Latin American Test Workshop, 2006
Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
From Nuclear Reaction to System Failures: Can We Address All Levels of Soft Errors Accurately?
Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006
2005
Proceedings of the VLSI-SoC: From Systems To Silicon, 2005
On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study.
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005
2004
J. Electron. Test., 2004
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004
Evaluation of Memory Built-in Self Repair Techniques for High Defect Density Technologie.
Proceedings of the 10th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2004), 2004
Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004
2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002
2001
Les limites technologiques du silicium et tolérance aux fautes. (Fault tolerance versus technological limitations of silicon).
PhD thesis, 2001
2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space Redundancy.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000
Proceedings of the 2000 Design, 2000
1999
Proceedings of the 17th IEEE VLSI Test Symposium (VTS '99), 1999