John A. Waicukauski

According to our database1, John A. Waicukauski authored at least 43 papers between 1981 and 2018.

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Bibliography

2018
XLBIST: X-Tolerant Logic BIST.
Proceedings of the IEEE International Test Conference, 2018

2017
A New Paradigm for Synthesis of Linear Decompressors.
Proceedings of the 54th Annual Design Automation Conference, 2017

2014
Achieving extreme scan compression for SoC Designs.
Proceedings of the 2014 International Test Conference, 2014

2013
Improving test generation by use of majority gates.
Proceedings of the 31st IEEE VLSI Test Symposium, 2013

Two-level compression through selective reseeding.
Proceedings of the 2013 IEEE International Test Conference, 2013

2012
Enhancing testability by structured partial scan.
Proceedings of the 30th IEEE VLSI Test Symposium, 2012

Hybrid selector for high-X scan compression.
Proceedings of the 2012 IEEE International Test Conference, 2012

2010
Increasing PRPG-based compression by delayed justification.
Proceedings of the 2011 IEEE International Test Conference, 2010

Highly efficient parallel ATPG based on shared memory.
Proceedings of the 2011 IEEE International Test Conference, 2010

Fully X-tolerant, very high scan compression.
Proceedings of the 47th Design Automation Conference, 2010

2008
Increasing Scan Compression by Using X-chains.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Automated Design and Insertion of Optimal One-Hot Bus Encoders.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Minimizing the Impact of Scan Compression.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

Fully X-tolerant combinational scan compression.
Proceedings of the 2007 IEEE International Test Conference, 2007

2005
Hierarchical Compactor Design for Diagnosis in Deterministic Logic BIST.
Proceedings of the 23rd IEEE VLSI Test Symposium (VTS 2005), 2005

Efficient compression of deterministic patterns into multiple PRPG seeds.
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

2004
Scalable selector architecture for x-tolerant deterministic BIST.
Proceedings of the 41th Design Automation Conference, 2004

2003
X-Tolerant Compression And Application of Scan-ATPG Patterns In A BIST Architecture.
Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

Efficient compression and application of deterministic patterns in a logic BIST architecture.
Proceedings of the 40th Design Automation Conference, 2003

2002
Scan Test Data Volume Reduction in Multi-Clocked Designs with Safe Capture Technique.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

Effective diagnostics through interval unloads in a BIST environment.
Proceedings of the 39th Design Automation Conference, 2002

2001
Design of compactors for signature-analyzers in built-in self-test.
Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

2000
Optimizing the flattened test-generation model for very large designs.
Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

1999
Using Verilog simulation libraries for ATPG.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

1998
Defining ATPG rules checking in STIL.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Extracting gate-level networks from simulation tables.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

1997
Using ATPG for clock rules checking in complex scan design.
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997

A Unified Interface for Scan Test Generation Based on STIL.
Proceedings of the Proceedings IEEE International Test Conference 1997, 1997

1996
Testing "untestable" faults in three-state circuits.
Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Two-Dimensional Test Data Decompressor for Multiple Scan Designs.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

Test Generation for Ultra-Large Circuits Using ATPG Constraints and Test-Pattern Templates.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

A Universal Technique for Accelerating Simulation of Scan Test Patterns.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1990
On computing the sizes of detected delay faults.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

ATPG for ultra-large structured designs.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1989
A Method for Generating Weighted Random Test Patterns.
IBM J. Res. Dev., 1989

Failure diagnosis of structured VLSI.
IEEE Des. Test, 1989

1988
Fault Detection Effectiveness of Weighted Random Patterns.
Proceedings of the Proceedings International Test Conference 1988, 1988

What is the Path to Fast Fault Simulation?
Proceedings of the Proceedings International Test Conference 1988, 1988

1987
Transition Fault Simulation.
IEEE Des. Test, 1987

1986
Transition Fault Simulation by Parallel Pattern Single Fault Propagation.
Proceedings of the Proceedings International Test Conference 1986, 1986

1985
A Statistical Calculation of Fault Detection Probabilities By Fast Fault Simulation.
Proceedings of the Proceedings International Test Conference 1985, 1985

1983
An LSSD Pseudo Random Pattern Test System.
Proceedings of the Proceedings International Test Conference 1983, 1983

1981
Fault Diagnosis in an LSSD Environment.
Proceedings of the Proceedings International Test Conference 1981, 1981


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