Nak-Kyu Park
According to our database1,
Nak-Kyu Park
authored at least 5 papers
between 2008 and 2012.
Collaborative distances:
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Bibliography
2012
A 1.6 V 1.4 Gbp/s/pin Consumer DRAM With Self-Dynamic Voltage Scaling Technique in 44 nm CMOS Technology.
IEEE J. Solid State Circuits, 2012
2011
A 1.6V 1.4Gb/s/pin consumer DRAM with self-dynamic voltage-scaling technique in 44nm CMOS technology.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2009
A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
2008
A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008