Won-Joo Yun

According to our database1, Won-Joo Yun authored at least 16 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A 1.2 V 20 nm 307 GB/s HBM DRAM With At-Speed Wafer-Level IO Test Scheme and Adaptive Refresh Considering Temperature Distribution.
IEEE J. Solid State Circuits, 2017

2016
18.2 A 1.2V 20nm 307GB/s HBM DRAM with at-speed wafer-level I/O test scheme and adaptive refresh considering temperature distribution.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design of non-contact 2Gb/s I/O test methods for high bandwidth memory (HBM).
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
17.7 A digital DLL with hybrid DCC using 2-step duty error extraction and 180° phase aligner for 2.67Gb/S/pin 16Gb 4-H stack DDR4 SDRAM with TSVs.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2013
A 1.26mW/Gbps 8 locking cycles versatile all-digital CDR with TDC combined DLL.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
A 7Gb/s/link non-contact memory module for multi-drop bus system using energy-equipartitioned coupled transmission line.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2011

A 0.6V noise rejectable all-digital CDR with free running TDC for a pulse-based inductive-coupling interface.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

2010
A 7.7mW/1.0ns/1.35V delay locked loop with racing mode and OA-DCC for DRAM interface.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

2009
Coverage expandable current type code controlled DCC with TDC-based range selector.
IEICE Electron. Express, 2009

A 1.6V 3.3Gb/s GDDR3 DRAM with dual-mode phase- and delay-locked loop using power-noise management with unregulated power supply in 54nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder.
IEICE Electron. Express, 2008

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Multi-Slew-Rate Output Driver and Optimized Impedance-Calibration Circuit for 66nm 3.0Gb/s/pin DRAM Interface.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Proceedings of the ESSCIRC 2008, 2008


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