Dongsuk Shin

According to our database1, Dongsuk Shin authored at least 17 papers between 2006 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
2.4 A 7nm High-Performance and Energy-Efficient Mobile Application Processor with Tri-Cluster CPUs and a Sparsity-Aware NPU.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2018
Erratum: Energy-efficient heterogeneous memory system for mobile platforms [IEICE Electronics Express Vol. 14 (2017) No. 24 pp. 20171002].
IEICE Electron. Express, 2018

Bandwidth-aware DRAM page migration for heterogeneous mobile memory systems.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

2017
Energy-efficient heterogeneous memory system for mobile platforms.
IEICE Electron. Express, 2017

2011
A 3.57 Gb/s/pin Low Jitter All-Digital DLL With Dual DCC Circuit for GDDR3 DRAM in 54-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2011

2010
Frequency-independent fast-lock register-controlled DLL with wide-range duty cycle adjuster.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009
A Low-Jitter Open-Loop All-Digital Clock Generator With Two-Cycle Lock-Time.
IEEE Trans. Very Large Scale Integr. Syst., 2009

A 7 ps Jitter 0.053 mm<sup>2</sup> Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC.
IEEE J. Solid State Circuits, 2009

Coverage expandable current type code controlled DCC with TDC-based range selector.
IEICE Electron. Express, 2009

A Fast-lock Synchronous Multi-phase Clock Generator based on a Time-to-digital Converter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
A 4-bit 2GSamples/s parallel Flash ADC using comb-type reference ladder.
IEICE Electron. Express, 2008

Wide frequency range duty cycle correction circuit for DDR interface.
IEICE Electron. Express, 2008

A 0.1-to-1.5GHz 4.2mW All-Digital DLL with Dual Duty-Cycle Correction Circuit and Update Gear Circuit for DRAM in 66nm CMOS Technology.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 0.17-1.4GHz low-jitter all digital DLL with TDC-based DCC using pulse width detection scheme.
Proceedings of the ESSCIRC 2008, 2008

2007
A 7ps-Jitter 0.053mm2 Fast-Lock ADDLL with Wide-Range and High-Resolution All-Digital DCC.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Low-Jitter Open-Loop All-Digital Clock Generator with 2 Cycle Lock-Time.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
A New Energy x Delay-Aware Flip-Flop.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006


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