Naoyuki Hamanishi

According to our database, Naoyuki Hamanishi authored at least 3 papers between 2006 and 2010.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2010

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

IEICE Trans. Electron., 2010

2009

A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.

Tetsuro Matsuno, Daisuke Fujimoto, Daisuke Kosaka, Naoyuki Hamanishi, Ken Tanabe, Masazumi Shiochi, Makoto Nagata

Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2006

A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC.

Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe, João C. Vital

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006