Daisuke Fujimoto
Orcid: 0000-0001-9389-7977
According to our database1,
Daisuke Fujimoto
authored at least 34 papers
between 2003 and 2023.
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Bibliography
2023
Remote Fault Injection Attack against Cryptographic Modules via Intentional Electromagnetic Interference from an Antenna.
Proceedings of the 2023 Workshop on Attacks and Solutions in Hardware Security, 2023
2022
Constructing software countermeasures against instruction manipulation attacks: an approach based on vulnerability evaluation using fault simulator.
Clust. Comput., 2022
2021
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021
2020
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
Comparison of Pearson correlation coefficient and distance correlation in Correlation Power Analysis on Digital Multiplier.
Proceedings of the 43rd International Convention on Information, 2020
How to Code Data Integrity Verification Secure Against Single-Spot-Laser-Induced Instruction Manipulation Attacks.
Proceedings of the 17th IEEE/ACS International Conference on Computer Systems and Applications, 2020
2019
Electromagnetic Information Extortion from Electronic Devices Using Interceptor and Its Countermeasure.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019
Fundamental Study on the Effects of Connector Torque Value on the Change of Inductance at the Contact Boundary.
IEICE Trans. Electron., 2019
Proceedings of the Smart Card Research and Advanced Applications, 2019
Low-Latency Pairing Processor Architecture Using Fully-Unrolled Quotient Pipelining Montgomery Multiplier.
Proceedings of the Asian Hardware Oriented Security and Trust Symposium, 2019
2018
A Demonstration of a HT-Detection Method Based on Impedance Measurements of the Wiring Around ICs.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks.
J. Cryptol., 2017
IEICE Electron. Express, 2017
2016
A Novel Methodology for Testing Hardware Security and Trust Exploiting On-Chip Power Noise Measurements (Extended Version).
IACR Cryptol. ePrint Arch., 2016
Proceedings of the International SoC Design Conference, 2016
Laser irradiation on EEPROM sense amplifiers enhances side-channel leakage of read bits.
Proceedings of the 2016 IEEE Asian Hardware-Oriented Security and Trust, 2016
2015
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
A 1 mm Pitch 80 × 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan.
IEEE J. Solid State Circuits, 2015
Proceedings of the 52nd Annual Design Automation Conference, 2015
A novel methodology for testing hardware security and trust exploiting On-Chip Power noise Measurement.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
A DPA/DEMA/LEMA-resistant AES cryptographic processor with supply-current equalizer and micro EM probe sensor.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015
2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
EM Attack Is Non-Invasive? - Design Methodology and Validity Verification of EM Attack Sensor.
IACR Cryptol. ePrint Arch., 2014
A local EM-analysis attack resistant cryptographic engine with fully-digital oscillator-based tamper-access sensor.
Proceedings of the Symposium on VLSI Circuits, 2014
12.4 A 1mm-pitch 80×80-channel 322Hz-frame-rate touch sensor with two-step dual-mode capacitance scan.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the 2014 IEEE International Symposium on Hardware-Oriented Security and Trust, 2014
Physical Security Evaluation at an Early Design-Phase: A Side-Channel Aware Simulation Methodology.
Proceedings of the International Workshop on Engineering Simulations for Cyber-Physical Systems, 2014
On-Chip Monitoring for In-Place Diagnosis of Undesired Power Domain Problems in IC Chips.
Proceedings of the 23rd IEEE Asian Test Symposium, 2014
An intermittent-driven supply-current equalizer for 11x and 4x power-overhead savings in CPA-resistant 128bit AES cryptographic processor.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
2011
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
Proceedings of the HOST 2011, 2011
2010
IEICE Trans. Electron., 2010
2009
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
2003
Proceedings of the 2003 IEEE International Conference on Robotics and Automation, 2003