João C. Vital

According to our database, João C. Vital authored at least 18 papers between 1993 and 2006.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2006

Kickback noise reduction techniques for CMOS latched comparators.

Pedro M. Figueiredo, João C. Vital

IEEE Trans. Circuits Syst. II Express Briefs, 2006

A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADC.

Pedro M. Figueiredo, Paulo Cardoso, Ana Lopes, Carlos Fachada, Naoyuki Hamanishi, Ken Tanabe, João C. Vital

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

The MOS capacitor amplifier.

Pedro M. Figueiredo, João C. Vital

IEEE Trans. Circuits Syst. II Express Briefs, 2004

Averaging technique in flash analog-to-digital converters.

Pedro M. Figueiredo, João C. Vital

IEEE Trans. Circuits Syst. I Regul. Pap., 2004

Low kickback noise techniques for CMOS latched comparators.

Pedro M. Figueiredo, João C. Vital

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Termination of averaging networks in flash ADCs.

Pedro M. Figueiredo, João C. Vital

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2003

Analysis of the averaging technique in flash ADCs.

Pedro M. Figueiredo, João C. Vital

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

2002

A CMOS logarithmic pipeline A/D converter with a dynamic range of 80 dB.

Jorge Guilherme, João C. Vital, José E. Franca

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

2001

A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications.

Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

IC design automation from circuit level optimization to retargetable layout.

Xu Jingnan, J. Serras, M. Oliveira, R. Belo, M. Bugalho, João C. Vital, Nuno Horta, José E. Franca

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A true logarithmic analog-to-digital pipeline converter with 1.5 bit/stage and digital correction.

Jorge Guilherme, João C. Vital, José E. Franca

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Design considerations for high resolution pipeline ADCs in digital CMOS technology.

Jorge Guilherme, Pedro M. Figueiredo, Pedro Azevedo, Goncalo Minderico, Antonio Leal, João C. Vital, José E. Franca

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

A Skill-based library for retargetable embedded analog cores.

Xu Jingnan, João C. Vital, Nuno Horta

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

1999

RAPID-retargetability for reusability of application-driven quadrature D/A interface block design.

José E. Franca, Nuno Horta, M. Pereira, João C. Vital, Rafael Castro-López, Manuel Delgado-Restituto, Francisco V. Fernández, Ángel Rodríguez-Vázquez, J. Ramos, P. Santos

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

1995

Optimum Resolution-per-Stage in High-Speed Pipelined A/D Converters Using Self-Calibration.

João Goes, João C. Vital, José E. Franca

Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

1993

High-Speed A/D-D/A Conversion System with Flexible Testing Capabilities.

João C. Vital, José E. Franca

Proceedings of the Sixth International Conference on VLSI Design, 1993

Fully-digital Testability of a High-speed Conversion System.

João C. Vital, José E. Franca, Nuno S. Silva

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

A Concurrent Two-step Flash Analogue-to-digital Converter Architecture.

João C. Vital, José E. Franca

Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993