Daisuke Kosaka

According to our database1, Daisuke Kosaka authored at least 9 papers between 1988 and 2010.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2010
Modeling of Power Noise Generation in Standard-Cell Based CMOS Digital Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

An Arbitrary Digital Power Noise Generator Using 65 nm CMOS Technology.
IEICE Trans. Electron., 2010

2009
A 6-bit arbitrary digital noise emulator in 65nm CMOS technology.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A full chip integrated power and substrate noise analysis framework for mixed-signal SoC design.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

2007
Chip-Level Substrate Coupling Analysis with Reference Structures for Verification.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Evaluation of Isolation Structures against High-Frequency Substrate Coupling in Analog/Mixed-Signal Integrated Circuits.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

Chip-Level Substrate Noise Analysis with Emphasis of Vertical Impurity Profile for Isolation.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006
Equivalent circuit modeling of guard ring structures for evaluation of substrate crosstalk isolation.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

1988
Multi-axis Force Sensor Using Piezoresistors and a Plate-Like Structure.
Proceedings of the IEEE International Workshop on Intelligent Robots and Systems '88, Proceedings. IROS 1988, Tokyo, Japan, October 31, 1988


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