Narayanan Krishnamurthy

According to our database, Narayanan Krishnamurthy authored at least 13 papers between 1999 and 2019.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2019

Materials data analytics for 9% Cr family steel.

Vyacheslav N. Romanov, Narayanan Krishnamurthy, Amit K. Verma, Laura S. Bruckman, Roger H. French, Jennifer L. W. Carter, Jeffrey A. Hawk

Stat. Anal. Data Min., 2019

2005

A methodology for validation of microprocessors using symbolic simulation.

Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir

Int. J. Embed. Syst., 2005

2004

A Top-Down Methodology for Microprocessor Validation.

Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir

IEEE Des. Test Comput., 2004

Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir

IEEE Des. Test Comput., 2004

Towards The Complete Elimination of Gate/Switch Level Simulations.

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

2003

Formal Verification Successes at Motorola.

Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin

Formal Methods Syst. Des., 2003

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.

Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir

Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

2002

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?

Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.

Jayanta Bhadra, Narayanan Krishnamurthy

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001

Design and Development Paradigm for Industrial Formal Verification CAD Tools.

Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham

IEEE Des. Test Comput., 2001

2000

Validating PowerPC Microprocessor Custom Memories.

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham

IEEE Des. Test Comput., 2000

Validation of PowerPC(tm) Custom Memories using Symbolic Simulation.

Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

1999

Design and Evaluation of System-Level Checks for On-Line Control Flow Error Detection.

Zeyad Alkhalifa, V. S. S. Nair, Narayanan Krishnamurthy, Jacob A. Abraham

IEEE Trans. Parallel Distributed Syst., 1999