Jayanta Bhadra

According to our database1, Jayanta Bhadra authored at least 53 papers between 1999 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2019
Practices and Challenges for Achieving Functional Safety of Modern Automotive SoCs.
IEEE Des. Test, 2019

2017
Challenges and Trends in Modern SoC Design Verification.
IEEE Des. Test, 2017

Data-Driven Test Plan Augmentation for Platform Verification.
IEEE Des. Test, 2017

Guest Editors' Introduction: Emerging Challenges and Solutions in SoC Verification.
IEEE Des. Test, 2017

Extensibility in Automotive Security: Current Practice and Challenges: Invited.
Proceedings of the 54th Annual Design Automation Conference, 2017

Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery.
Proceedings of the 54th Annual Design Automation Conference, 2017

Feature extraction from design documents to enable rule learning for improving assertion coverage.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
Security challenges in mobile and IoT systems.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

Striking a balance between SoC security and debug requirements.
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016

2014
On application of data mining in functional debug.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.
J. Electron. Test., 2013

Novel test analysis to improve structural coverage - A commercial experiment.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

Process-variation-aware Iddq diagnosis for nano-scale CMOS designs - the first step.
Proceedings of the Design, Automation and Test in Europe, 2013

Simulation knowledge extraction and reuse in constrained random processor verification.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Introduction to special section on verification challenges in the concurrent world.
ACM Trans. Design Autom. Electr. Syst., 2012

Novel test detection to improve simulation efficiency - A commercial experiment.
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012

An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
A Unified Formal Framework for Analyzing Functional and Speed-path Properties.
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011

2010
Innovative practices session 7C: Verification and testing challenges in high-level synthesis.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

A kernel-based approach for functional test program generation.
Proceedings of the 2011 IEEE International Test Conference, 2010

Modeling and verification of industrial flash memories.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

2009
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

Portable simulation/emulation stimulus on an industrial-strength SoC.
Proceedings of the 2009 IEEE International Test Conference, 2009

Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning.
Proceedings of the 2009 IEEE International Test Conference, 2009

Synthesis Oriented Scheduling of Multiparty Rendezvous in Transaction Level Models.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

On soft error rate analysis of scaled CMOS designs - A statistical perspective.
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

Accelerating multi-party scheduling for transaction-level modeling.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008
Validating Power Architecture<sup>TM</sup> Technology-Based MPSoCs Through Executable Specifications.
IEEE Trans. Very Large Scale Integr. Syst., 2008

2007
A Survey of Hybrid Techniques for Functional Verification.
IEEE Des. Test Comput., 2007

Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Des. Test Comput., 2007

Enhancing signal controllability in functional test-benches through automatic constraint extraction.
Proceedings of the 2007 IEEE International Test Conference, 2007

An incremental learning framework for estimating signal controllability in unit-level verification.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

A Mechanized Refinement Framework for Analysis of Custom Memories.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
A Trace-Driven Validation Methodology for Multi-Processor SOCS.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006

2005
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.
Formal Methods Syst. Des., 2005

Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005

Establishing latch correspondence for embedded circuits of PowerPC microprocessors.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.
IEEE Des. Test Comput., 2004

Towards The Complete Elimination of Gate/Switch Level Simulations.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Formal Verification of a System-on-Chip Using Computation Slicing.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

2003
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test., 2003

Model Checking of Security Protocols with Pre-configuration.
Proceedings of the Information Security Applications, 4th International Workshop, 2003

A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003

2002
Program Slicing for Hierarchical Test Generation.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

2001
A language formalism for verification of PowerPC<sup>TM</sup> custom memories using compositions of abstract specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

Full chip false timing path identification: applications to the PowerPCTM microprocessors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Using Abstract Specifications to Verify PowerPC<sup>TM</sup> Custom Memories by Symbolic Trajectory Evaluation.
Proceedings of the Correct Hardware Design and Verification Methods, 2001

2000
Automatic Validation Test Generation Using Extracted Control Models.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

1999
Improving Witness Search Using Orders on States.
Proceedings of the IEEE International Conference On Computer Design, 1999


  Loading...