Jayanta Bhadra
Affiliations:- University of Texas at Austin, USA
According to our database1,
Jayanta Bhadra
authored at least 54 papers
between 1999 and 2019.
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Bibliography
2019
IEEE Des. Test, 2019
2017
IEEE Des. Test, 2017
Proceedings of the 54th Annual Design Automation Conference, 2017
Learning to Produce Direct Tests for Security Verification Using Constrained Process Discovery.
Proceedings of the 54th Annual Design Automation Conference, 2017
Feature extraction from design documents to enable rule learning for improving assertion coverage.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017
2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
Proceedings of the 29th IEEE International System-on-Chip Conference, 2016
2014
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014
2013
Guest Editorial: Test and Verification Challenges for Future Microprocessors and SoC Designs.
J. Electron. Test., 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Simulation knowledge extraction and reuse in constrained random processor verification.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
2012
ACM Trans. Design Autom. Electr. Syst., 2012
Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, 2012
An intelligent analysis of Iddq data for chip classification in very deep-submicron (VDSM) CMOS technology.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Proceedings of the 12th International Workshop on Microprocessor Test and Verification, 2011
2010
Innovative practices session 7C: Verification and testing challenges in high-level synthesis.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010
Proceedings of the 2011 IEEE International Test Conference, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009
Proceedings of the 2009 IEEE International Test Conference, 2009
Speeding up bounded sequential equivalence checking with cross-timeframe state-pair constraints from data learning.
Proceedings of the 2009 IEEE International Test Conference, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
2008
Validating Power Architecture<sup>TM</sup> Technology-Based MPSoCs Through Executable Specifications.
IEEE Trans. Very Large Scale Integr. Syst., 2008
2007
IEEE Des. Test Comput., 2007
Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques.
IEEE Des. Test Comput., 2007
Enhancing signal controllability in functional test-benches through automatic constraint extraction.
Proceedings of the 2007 IEEE International Test Conference, 2007
An incremental learning framework for estimating signal controllability in unit-level verification.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007
2006
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006
Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study.
Proceedings of the Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), 2006
2005
A Formal Framework for Verification of Embedded Custom Memories of the Motorola MPC7450 Microprocessor.
Formal Methods Syst. Des., 2005
Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors.
Proceedings of the Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), 2005
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005
2004
Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation.
IEEE Des. Test Comput., 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004
2003
A Hierarchical Test Generation Approach Using Program Slicing Techniques on Hardware Description Languages.
J. Electron. Test., 2003
Proceedings of the Information Security Applications, 4th International Workshop, 2003
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits.
Proceedings of the Fourth International Workshop on Microprocessor Test and Verification, 2003
2002
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs?
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002
Automatic Generation of Design Constraints in Verifying High Performance Embedded Dynamic Circuits.
Proceedings of the Proceedings IEEE International Test Conference 2002, 2002
2001
A language formalism for verification of PowerPC<sup>TM</sup> custom memories using compositions of abstract specifications.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001
Full chip false timing path identification: applications to the PowerPCTM microprocessors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Using Abstract Specifications to Verify PowerPC<sup>TM</sup> Custom Memories by Symbolic Trajectory Evaluation.
Proceedings of the Correct Hardware Design and Verification Methods, 2001
2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
A quick and inexpensive method to identify false critical paths using ATPG techniques: an experiment with a PowerPC<sup>TM</sup> microprocessor.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Proceedings of the IEEE International Conference On Computer Design, 1999