Natalino G. Busá

According to our database1, Natalino G. Busá authored at least 7 papers between 2000 and 2003.

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Bibliography

2003
Reconfigurable Instruction-Set Application-Tuning for DSP.
J. Circuits Syst. Comput., 2003

2002
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems.
Des. Autom. Embed. Syst., 2002

RAPIDO: A Modular, Multi-Board, Heterogeneous Multi-Processor, PCI Bus Based Prototyping Framework for the Validation of SoC VLSI Designs.
Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

2001
Synthesizing A Long Latency Unit Within Vliw Processor.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Functional units with conditional input/output behavior in VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Scheduling Coarse-Grain Operations for VLIW Processors.
Proceedings of the 13th International Symposium on System Synthesis, 2000


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