Anshul Kumar

According to our database, Anshul Kumar authored at least 99 papers between 1980 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

A survey on emotion-cause extraction in psychological text using deep learning methods.

Anshul Kumar, Ankit Kumar Jain

Prog. Artif. Intell., December, 2023

Cost Optimization of an Unreliable server queue with two stage service process under hybrid vacation policy.

Anshul Kumar, Madhu Jain

Math. Comput. Simul., 2023

2022

Game Theory-Based Parameter Tuning for Energy-Efficient Path Planning on Modern UAVs.

Diksha Moolchandani, Kishore Yadav, Geesara Kulathunga, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti Sarangi

ACM Trans. Cyber Phys. Syst., 2022

Performance and Power Prediction for Concurrent Execution on GPUs.

Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi

ACM Trans. Archit. Code Optim., 2022

Emotion detection in psychological texts by fine-tuning BERT using emotion-cause pair extraction.

Anshul Kumar, Ankit Kumar Jain

Int. J. Speech Technol., 2022

Effect of disaster and balking on M/M/1 driven fluid queue with working vacation.

Madhu Jain, Anshul Kumar

Int. J. Math. Oper. Res., 2022

Minimizing Off-Chip Memory Access for CNN Accelerators.

Saurabh Tewari, Anshul Kumar, Kolin Paul

IEEE Consumer Electron. Mag., 2022

PredStereo: An Accurate Real-time Stereo Vision System.

Diksha Moolchandani, Nivedita Shrivastava, Anshul Kumar, Smruti R. Sarangi

Proceedings of the IEEE/CVF Winter Conference on Applications of Computer Vision, 2022

SACC: Split and Combine Approach to Reduce the Off-chip Memory Accesses of LSTM Accelerators.

Saurabh Tewari, Anshul Kumar, Kolin Paul

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Performance-Energy Trade-off in Modern CMPs.

Solomon Abera, M. Balakrishnan, Anshul Kumar

ACM Trans. Archit. Code Optim., 2021

Accelerating CNN Inference on ASICs: A Survey.

Diksha Moolchandani, Anshul Kumar, Smruti R. Sarangi

J. Syst. Archit., 2021

The application of predictive analytics to identify at-risk students in health professions education.

Anshul Kumar, Roger Edwards, Lisa Walker

CoRR, 2021

Game Theory-Based Parameter-Tuning for Path Planning of UAVs.

Diksha Moolchandani, Geesara Prathap, Ilya Afanasyev, Anshul Kumar, Manuel Mazzara, Smruti R. Sarangi

Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

2020

VisSched: An Auction-Based Scheduler for Vision Workloads on Heterogeneous Processors.

Diksha Moolchandani, Anshul Kumar, José F. Martínez, Smruti R. Sarangi

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Bus Width Aware Off-Chip Memory Access Minimization for CNN Accelerators.

Saurabh Tewari, Anshul Kumar, Kolin Paul

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Performance Prediction for Multi-Application Concurrency on GPUs.

Diksha Moolchandani, Sudhanshu Gupta, Anshul Kumar, Smruti R. Sarangi

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2020

2019

ML Guided Energy-Performance Trade-Off Estimation For Uncore Frequency Scaling.

Solomon Abera Bekele, M. Balakrishnan, Anshul Kumar

Proceedings of the 2019 Spring Simulation Conference, 2019

2018

Performance-Energy Trade-off in CMPs with Per-Core DVFS.

Solomon Abera, M. Balakrishnan, Anshul Kumar

Proceedings of the Architecture of Computing Systems - ARCS 2018, 2018

2017

PLSS: A Scheduler for Multi-core Embedded Systems.

Solomon Abera, M. Balakrishnan, Anshul Kumar

Proceedings of the Architecture of Computing Systems - ARCS 2017, 2017

2016

Impact of crosstalk and process variation on capture power reduction for at-speed test.

Surya Piplani, G. S. Visweswaran, Anshul Kumar

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

2014

Shared-port register file architecture for low-energy VLIW processors.

Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda

ACM Trans. Archit. Code Optim., 2014

2013

High performance 3D-FFT implementation.

U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

Exploiting UML based validation for compliance checking of TLM 2 based models.

Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda

Des. Autom. Embed. Syst., 2012

2011

Strap-down Pedestrian Dead-Reckoning system.

Pragun Goyal, Vinay J. Ribeiro, Huzur Saran, Anshul Kumar

Proceedings of the 2011 International Conference on Indoor Positioning and Indoor Navigation, 2011

A UML based framework for efficient validation of TLM 2 models.

Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda

Proceedings of the 2011 Forum on Specification & Design Languages, 2011

A SysML Profile for Development and Early Validation of TLM 2.0 Models.

Vaibhav Jain, Anshul Kumar, Preeti Ranjan Panda

Proceedings of the Modelling Foundations and Applications - 7th European Conference, 2011

Exploiting temporal decoupling to accelerate trace-driven NoC emulation.

Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar

Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

2010

Front-End Design Flows for Systems on Chip: An Embedded Tutorial.

Anshul Kumar, Preeti Ranjan Panda

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

Instruction Selection in ASIP Synthesis Using Functional Matching.

Nidhi Arora, Kiran Chandramohan, Nagaraju Pothineni, Anshul Kumar

Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

FastFwd: an efficient hardware acceleration technique for trace-driven network-on-chip simulation.

Gummidipudi Krishnaiah, B. V. N. Silpa, Preeti Ranjan Panda, Anshul Kumar

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

A high-level synthesis flow for custom instruction set extensions for application-specific processors.

Nagaraju Pothineni, Philip Brisk, Paolo Ienne, Anshul Kumar, Kolin Paul

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

An Index-Based Mobile Checkpointing and Recovery Algorithm.

Awadhesh Kumar Singh, Rohit Bhat, Anshul Kumar

Proceedings of the Distributed Computing and Networking, 10th International Conference, 2009

2008

A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.

Nagaraju Pothineni, Anshul Kumar, Kolin Paul

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.

Nagaraju Pothineni, Anshul Kumar, Kolin Paul

Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

2007

Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures.

Anup Gangwar, M. Balakrishnan, Anshul Kumar

ACM Trans. Design Autom. Electr. Syst., 2007

Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures.

Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar

Int. J. Parallel Program., 2007

Application Specific Datapath Extension with Distributed I/O Functional Units.

Nagaraju Pothineni, Anshul Kumar, Kolin Paul

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Power Reduction in VLIW Processor with Compiler Driven Bypass Network.

Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Recurring Pattern Identification and its Application to Instruction Set Extension.

Nagaraju Pothineni, Anshul Kumar, Kolin Paul

Proceedings of the 2007 International Conference on Computer Design, 2007

2006

Rapid Resource-Constrained Hardware Performance Estimation.

Basant Kumar Dwivedi, Arun Kejariwal, M. Balakrishnan, Anshul Kumar

Proceedings of the 17th IEEE International Workshop on Rapid System Prototyping (RSP 2006), 2006

Battery aware dynamic scheduling for periodic task graphs.

Venkat Rao, Nicolas Navet, Gaurav Singhal, Anshul Kumar, G. S. Visweswaran

Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005

Battery Model for Embedded Systems.

Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas Navet

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Integrated On-Chip Storage Evaluation in ASIP Synthesis.

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar

Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

2004

An efficient technique for exploring register file size in ASIP design.

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture.

Sourabh Saluja, Anshul Kumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Real Time Dynamic Voltage Scaling For Embedded Systems.

Venkat Rao, Gaurav Singhal, Anshul Kumar

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Synthesis of Application Specific Multiprocessor Architectures for Process Networks.

Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan

Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units.

Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne

Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

Automatic synthesis of system on chip multiprocessor architectures for process networks.

Basant Kumar Dwivedi, Anshul Kumar, M. Balakrishnan

Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

2003

Hybrid Multi-FPGA Board Evaluation by Permitting Limited Multi-Hop Routing.

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar

Des. Autom. Embed. Syst., 2003

SoC Synthesis with Automatic Hardware Software Interface Generation.

Amarjeet Singh, Amit Chhabra, Anup Gangwar, Basant Kumar Dwivedi, M. Balakrishnan, Anshul Kumar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Design of a 2D DCT/IDCT application specific VLIW processor supporting scaled and sub-sampled blocks.

Rohini Krishnan, Om Prakash Gangwal, Jos T. J. van Eijndhoven, Anshul Kumar

Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Exploring Storage Organization in ASIP Synthesis.

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar

Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

2002

A New Divide and Conquer Method for Achieving High Speed Division in Hardware.

Murali Mohan, Rohini Krishnan, Anshul Kumar, M. Balakrishnan

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Exploring the Number of Register Windows in ASIP Synthesis.

Vishal P. Bhatt, M. Balakrishnan, Anshul Kumar

Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002

Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar

Proceedings of the 13th IEEE International Workshop on Rapid System Prototyping (RSP 2002), 2002

A New Performance Evaluation Approach for System Level Design Space Exploration.

M. Balakrishnan, Anshul Kumar, C. P. Joshi

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

A Trimaran Based Framework for Exploring the Design Space of VLIW ASIPs with Coarse Grain Functional Units.

M. Balakrishnan, Anshul Kumar, Paolo Ienne, Anup Gangwar, Bhuvan Middha

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Multi-hop routing of multi-terminal nets for evaluation of hybrid multi-FPGA boards.

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

An efficient technique for exploring register file size in ASIP synthesis.

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar

Proceedings of the International Conference on Compilers, 2002

2001

Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study.

Anupam Rastogi, M. Balakrishnan, Anshul Kumar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

ASIP Design Methodologies : Survey and Issues.

Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Synthesizing A Long Latency Unit Within Vliw Processor.

Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

2000

Grammar-based hardware synthesis from port-size independent specifications.

Johnny Öberg, Anshul Kumar, Ahmed Hemani

IEEE Trans. Very Large Scale Integr. Syst., 2000

A scheme for multiple on-chip signature checking for embedded SRAMS.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Syst. Archit., 2000

nterface Synthesis: Issues and Approaches.

Arvind Rajawat, M. Balakrishnan, Anshul Kumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Evaluation of Various Routing Architectures for Multi-FPGA Boards.

Sushil Chandra Jain, Shashi Kumar, Anshul Kumar

Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000

Efficient Embedding of Partitioned Circuits onto Multi-FPGA Boards.

Sushil Chandra Jain, Anshul Kumar, Shashi Kumar

Proceedings of the Field-Programmable Logic and Applications, 2000

1999

Built-in Self Test Based on Multiple On-Chip Signature Checking.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Electron. Test., 1999

1998

Direct mapping of RTL structures onto LUT-based FPGA's.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Optimization of Mutual and Signature Testing Schemes for Highly Concurrent Systems.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

J. Electron. Test., 1998

An Object-Oriented Concept for Intelligent Library Functions.

Johnny Öberg, Axel Jantsch, Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Speeding Up Program Execution Using Reconfigurable Hardware and a Hardware Function Library.

Sitanshu Jain, M. Balakrishnan, Anshul Kumar, Shashi Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

On-Chip Signature Checking for Embedded Memories.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Hybrid Testing Schemes Based on Mutual and Signature Testing.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

Specification of Exception Handling in Grammar-Based Hardware Synthesis.

Johnny Öberg, Anshul Kumar, Ahmed Hemani

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols.

Johnny Öberg, Ahmed Hemani, Anshul Kumar

Proceedings of the 1998 Design, 1998

1997

Optimal Clock Period for Synthesized Data Paths.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

Efficient Implementation of Multiple On-Chip Signature Checking.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

A multiplier generator for Xilinx FPGAs.

Jaswinder Pal Singh, Anshul Kumar, Shashi Kumar

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A Novel BIST Architecture With Built-in Self Check.

Mohammed Fadle Abdulla, C. P. Ravikumar, Anshul Kumar

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Grammar-Based Hardware Synthesis of Data Communication Protocols.

Johnny Öberg, Anshul Kumar, Ahmed Hemani

Proceedings of the 9th International Symposium on System Synthesis, 1996

1995

An HOL based framework for design of correct high level synthesizers.

B. M. Subraya, Anshul Kumar, Shashi Kumar

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Heuristic search based approach to scheduling, allocation and binding in Data Path Synthesis.

Alok Kumar, Anshul Kumar, M. Balakrishnan

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

Circuit partitioning with partial order for mixed simulation emulation environment.

Gurmeet Singh Manku, Anshul Kumar, Shashi Kumar

Proceedings of the Sixth IEEE International Workshop on Rapid System Prototyping (RSP '95), 1995

Delay Minimal Mapping of RTL Structures onto LUT Based FPGAs.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Field-Programmable Logic and Applications, 5th International Workshop, 1995

1994

FAST: FPGA Targeted RTL Structure Synthesis Technique.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Seventh International Conference on VLSI Design, 1994

An Efficient Technique for Mapping RTL Structures onto FPGAs.

A. R. Naseer, M. Balakrishnan, Anshul Kumar

Proceedings of the Field-Programmable Logic, 1994

1993

DESSERT: Design Space Exploration of RT Level Components.

M. V. Rao, M. Balakrishnan, Anshul Kumar

Proceedings of the Sixth International Conference on VLSI Design, 1993

High Level Design Experiences with IDEAS.

C. S. Ajay, M. Balakrishnan, D. Harikrishna, M. Karunakaran, Anshul Kumar, Shashi Kumar, V. Mudgil, A. R. Naseer

Proceedings of the Sixth International Conference on VLSI Design, 1993

1992

Data Path Synthesis With Global Time Constraint.

Prashant P. Nedungadi, M. Balakrishnan, Anshul Kumar

Proceedings of the Fifth International Conference on VLSI Design, 1992

A Partitioning Scheme For Multiple Pla Based Control Part Synthesis In Ideas.

Manu Lauria, Shashi Kumar, Anshul Kumar

Proceedings of the Fifth International Conference on VLSI Design, 1992

1989

Ideas: a tool for VLSI CAD.

Alok Kumar, Vijeta Kashyap, Sunil D. Sherlekar, G. Venkatesh, S. Biswas, Anshul Kumar, P. C. P. Bhatt, Sashi Kumar

IEEE Des. Test, 1989

Automatic Synthesis of Microprogrammed Control Units from Behavioral Descriptions.

Anshul Kumar, Shashi Kumar, P. Kulshreshtha, Sudipto Ghose

Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989

1986

Automatic Generation of Digital System Schematic Diagrams.

Anshul Kumar, Anjali Arya, V. V. Swaminathan, Amit Misra

IEEE Des. Test, 1986

1985

An automated data path synthesizer for a canonic structure, implementable in VLSI.

Kumar Ramayya, Anshul Kumar, Surendra Prasad

Proceedings of the 22nd ACM/IEEE conference on Design automation, 1985

1984

Recognition of consonants using an ARMA model of the speech signal.

Anshul Kumar, George A. Bekey

Proceedings of the IEEE International Conference on Acoustics, 1984

1983

A methodology for custom VLSI layout.

Melvin A. Breuer, Anshul Kumar

IEEE Trans. Syst. Man Cybern., 1983

1980

A Structured Language for CAD of Digital Systems.

Anshul Kumar, P. C. P. Bhatt

Proceedings of the 7th Annual Symposium on Computer Architecture, 1980