Kees Goossens

According to our database1, Kees Goossens authored at least 176 papers between 1992 and 2019.

Collaborative distances:
  • Dijkstra number2 of two.
  • Erdős number3 of three.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepages:

On csauthors.net:

Bibliography

2019
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.
IEEE Trans. VLSI Syst., 2019

Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms.
ACM Trans. Design Autom. Electr. Syst., 2019

Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs.
IEEE Trans. Industrial Informatics, 2019

A Scalable and Fast Model for Performance Analysis of IEEE 802.15.4 TSCH Networks.
Proceedings of the 30th IEEE Annual International Symposium on Personal, 2019

Defect-Location Identification for Cell-Aware Test.
Proceedings of the IEEE Latin American Test Symposium, 2019

Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.
Proceedings of the IEEE International Test Conference in Asia, 2019

Component-Level ASIL Decomposition for Automotive Architectures.
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2019

Model-Based Processor-in-the-Loop Framework for Composable Multi-core Platforms.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

Chip Health Tracking Using Dynamic In-Situ Delay Monitoring.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Delay-based Design of Feedforward Tracking Control for Predictable Embedded Platforms.
Proceedings of the 2019 American Control Conference, 2019

2018
Dependable Interference-Aware Time-Slotted Channel Hopping for Wireless Sensor Networks.
TOSN, 2018

Guard-Time Design for Symmetric Synchronization in IEEE 802.15.4 Time-Slotted Channel Hopping.
Proceedings of the 87th IEEE Vehicular Technology Conference, 2018

A Generic Method for a Bottom-Up ASIL Decomposition.
Proceedings of the Computer Safety, Reliability, and Security, 2018

Hybrid Timeslot Design for IEEE 802.15.4 TSCH to Support Heterogeneous WSNs.
Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018

A Unified Programming Model for Time- and Data-Driven Embedded Applications.
Proceedings of the 26th Euromicro International Conference on Parallel, 2018

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

Fault-Tolerant Deployment of Dataflow Applications Using Virtual Processors.
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018

2017
NoC-Based Multiprocessor Architecture for Mixed-Time-Criticality Applications.
Proceedings of the Handbook of Hardware/Software Codesign., 2017

A Globally Arbitrated Memory Tree for Mixed-Time-Criticality Systems.
IEEE Trans. Computers, 2017

Time synchronization for an emulated CAN device on a Multi-Processor System on Chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2017

An analytical model for interdependent setup/hold-time characterization of flip-flops.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Programming and analysing scenario-aware dataflow on a multi-processor platform.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Efficient synchronization methods for LET-based applications on a Multi-Processor System on Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation.
IEEE Trans. VLSI Syst., 2016

Power/Performance Trade-Offs in Real-Time SDRAM Command Scheduling.
IEEE Trans. Computers, 2016

Architecture and analysis of a dynamically-scheduled real-time memory controller.
Real-Time Systems, 2016

Cloud-based Design and Virtual Prototyping Environment for Embedded Systems.
Int. J. Online Eng., 2016

RTOS acceleration in an MPSoC with reconfigurable hardware.
Computers & Electrical Engineering, 2016

Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016

An Experimental Study of Cross-Technology Interference in In-Vehicle Wireless Sensor Networks.
Proceedings of the 19th ACM International Conference on Modeling, 2016

An embedded CAN controller for a vehicle networking course project.
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016

Resource utilization and Quality-of-Control trade-off for a composable platform.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation.
ACM Trans. Embedded Comput. Syst., 2015

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels.
ACM Trans. Embedded Comput. Syst., 2015

Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures.
Microprocessors and Microsystems - Embedded Hardware Design, 2015

T-CREST: Time-predictable multi-core architecture for embedded systems.
Journal of Systems Architecture - Embedded Systems Design, 2015

Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC.
Journal of Systems Architecture - Embedded Systems Design, 2015

Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015

Enhanced Time-Slotted Channel Hopping in WSNs Using Non-intrusive Channel-Quality Estimation.
Proceedings of the 12th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2015

Mode-controlled data-flow modeling of real-time memory controllers.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Distributed power management of real-time applications on a GALS multiprocessor SOC.
Proceedings of the 2015 International Conference on Embedded Software, 2015

Run-time middleware to support real-time system scenarios.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Composable Platform-Aware Embedded Control Systems on a Multi-core Architecture.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A Scenario-Aware Dataflow Programming Model.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs.
ACM Trans. Embedded Comput. Syst., 2014

dAElite: A TDM NoC Supporting QoS, Multicast, and Fast Connection Set-Up.
IEEE Trans. Computers, 2014

Hardware Task-Status Manager for an RTOS with FIFO communication.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Dynamic Command Scheduling for Real-Time Memory Controllers.
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014

Composable and Predictable Dynamic Loading for Time-Critical Partitioned Systems.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

CoMik: A predictable and cycle-accurately composable real-time microkernel.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Review, 2013

A hardware/software platform for QoS bridging over multi-chip NoC-based systems.
Parallel Computing, 2013

TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip.
Microprocessors and Microsystems - Embedded Hardware Design, 2013

A unified execution model for multiple computation models of streaming applications on a composable MPSoC.
Journal of Systems Architecture - Embedded Systems Design, 2013

Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors.
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013

A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013

Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variation.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013

Run-Time Slack Distribution for Real-Time Data-Flow Applications on Embedded MPSoC.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Router Designs for an Asynchronous Time-Division-Multiplexed Network-on-Chip.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

A General Framework for Average-Case Performance Analysis of Shared Resources.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Conservative open-page policy for mixed time-criticality memory controllers.
Proceedings of the Design, Automation and Test in Europe, 2013

Architecture and optimal configuration of a real-time multi-channel memory controller.
Proceedings of the Design, Automation and Test in Europe, 2013

System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013

Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A reconfigurable real-time SDRAM controller for mixed time-criticality systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

2012
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.
IET Computers & Digital Techniques, 2012

Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays.
IET Computers & Digital Techniques, 2012

Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012

Hardware design and implementation of a Network-on-Chip based load balancing switch fabric.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Architecture and design flow for a debug event distribution interconnect.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012

Power versus quality trade-offs for adaptive real-time applications.
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012

A Predictor-Based Power-Saving Policy for DRAM Memories.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Composable Virtual Memory for an Embedded SoC.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

A TDM NoC supporting QoS, multicast, and fast connection set-up.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Memory-map selection for firm real-time SDRAM controllers.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

DRAM selection and configuration for real-time mobile systems.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Run-time power-down strategies for real-time SDRAM memory controllers.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Hardware / Software Virtualization for the Reconfigurable Multicore Platform.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
A TDM slot allocation flow based on multipath routing in NoCs.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Design and implementation of an operating system for composable processor sharing.
Microprocessors and Microsystems - Embedded Hardware Design, 2011

Interactive Debug of SoCs with Multiple Clocks.
IEEE Design & Test of Computers, 2011

A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications.
Design Autom. for Emb. Sys., 2011

Special Issue on Networks-on-Chips: Design Flows and Case Studies.
Design Autom. for Emb. Sys., 2011

Composable power management with energy and power budgets per application.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Automatic Generation of Efficient Predictable Memory Patterns.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011

Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011

Time-predictable and composable architectures for dependable embedded systems.
Proceedings of the 11th International Conference on Embedded Software, 2011

A Non-Intrusive Online FPGA Test Scheme Using a Hardwired Network on Chip.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Power Minimisation for Real-Time Dataflow Applications.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

A Unified Execution Model for Data-Driven Applications on a Composable MPSoC.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Improved Power Modeling of DDR SDRAMs.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

Optimal scheduling of switched FlexRay networks.
Proceedings of the Design, Automation and Test in Europe, 2011

An FPGA bridge preserving traffic quality of service for on-chip network-based systems.
Proceedings of the Design, Automation and Test in Europe, 2011

Architectures and modeling of predictable memory controllers for improved system integration.
Proceedings of the Design, Automation and Test in Europe, 2011

Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011

Composable local memory organisation for streaming applications on embedded MPSoCs.
Proceedings of the 8th Conference on Computing Frontiers, 2011

Composability and Predictability for Independent Application Development, Verification, and Execution.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Bandwidth Analysis of Functional Interconnects Used as Test Access Mechanism.
J. Electronic Testing, 2010

On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Classification and Analysis of Predictable Memory Patterns.
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010

Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010

A distributed architecture to check global properties for post-silicon debug.
Proceedings of the 15th European Test Symposium, 2010

Conservative application-level performance analysis through simulation of MPSoCs.
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010

Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

The aethereal network on chip after ten years: goals, evolution, lessons, and future.
Proceedings of the 47th Design Automation Conference, 2010

Buffered Crossbar Fabrics Based on Networks on Chip.
Proceedings of the 8th Annual Conference on Communication Networks and Services Research, 2010

2009
CoMPSoC: A template for composable and predictable multi-processor system on chips.
ACM Trans. Design Autom. Electr. Syst., 2009

Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis.
IET Computers & Digital Techniques, 2009

Networks on chips [editorial].
IET Computers & Digital Techniques, 2009

Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009

Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Modeling reconfiguration in a FPGA with a hardwired network on chip.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009

Efficient Multicast Support in Buffered Crossbars using Networks on Chip.
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009

Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Internet-Router Buffered Crossbars Based on Networks on Chip.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Composable Resource Sharing Based on Latency-Rate Servers.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009

Aelite: A flit-synchronous Network on Chip with composable and predictable services.
Proceedings of the Design, Automation and Test in Europe, 2009

A high-level debug environment for communication-centric debug.
Proceedings of the Design, Automation and Test in Europe, 2009

An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009

2008
A monitoring-aware network-on-chip design flow.
Journal of Systems Architecture - Embedded Systems Design, 2008

Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008

Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008

Bandwidth Analysis for Reusing Functional Interconnect as Test Access Mechanism.
Proceedings of the 13th European Test Symposium, 2008

You can catch more bugs with transaction level honey.
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008

2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.
VLSI Design, 2007

Avoiding Message-Dependent Deadlock in Network-Based Systems on Chip.
VLSI Design, 2007

Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Computers & Digital Techniques, 2007

Trade-offs in the Configuration of a Network on Chip for Multiple Use-Cases.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Transaction-Based Communication-Centric Debug.
Proceedings of the First International Symposium on Networks-on-Chips, 2007

Communication-Centric SoC Debug Using Transactions.
Proceedings of the 12th European Test Symposium, 2007

Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Congestion-controlled best-effort communication for networks-on-chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

Predator: a predictable SDRAM memory controller.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
Proceedings of the IFIP VLSI-SoC 2006, 2006

Transaction Monitoring in Networks on Chip: The On-Chip Run-Time Perspective.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

NoC monitoring: impact on the design flow.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism.
Proceedings of the 11th European Test Symposium, 2006

Networks on chips for high-end consumer-electronics TV system architectures.
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006

A methodology for mapping multiple use-cases onto networks on chips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

Mapping and configuration methods for multi-use-case networks on chips.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
An event-based monitoring service for networks on chip.
ACM Trans. Design Autom. Electr. Syst., 2005

An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Æthereal Network on Chip: Concepts, Architectures, and Implementations.
IEEE Design & Test of Computers, 2005

A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005

A unified approach to constrained mapping and routing on network-on-chip architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Deadlock Prevention in the Æthereal Protocol.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Formal Methods for Networks on Chips.
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005

2004
An event-based network-on-chip monitoring service.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
Proceedings of the 2004 Design, 2004

Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach.
Proceedings of the 2004 Design, 2004

2003
Bringing communication networks on a chip: test and verification implications.
IEEE Communications Magazine, 2003

Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
Proceedings of the 2003 Design, 2003

Guaranteeing the Quality of Services in Networks on Chip.
Proceedings of the Networks on Chip, 2003

2002
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems.
Design Autom. for Emb. Sys., 2002

Networks on Silicon: Blessing or Nightmare?
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002

Networks on Silicon: Combining Best-Effort and Guaranteed Services.
Proceedings of the 2002 Design, 2002

The Cost of Communication Protocols and Coordination Languages in Embedded Systems.
Proceedings of the Coordination Models and Languages, 5th International Conference, 2002

2001
A protocol and memory manager for on-chip communication.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

1998
The petrol approach to high-level power estimation.
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998

1995
Reasoning about VHDL using operational and observational semantics.
Proceedings of the Correct Hardware Design and Verification Methods, 1995

1993
Stucture and Behaviour in Hardware Verification.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993

Embedding hardware description languages in proof systems.
PhD thesis, 1993

1992
Operational Semantics Based on Formal Symbolic Simulation.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992


  Loading...