Kees Goossens
Orcid: 0000-0001-7536-4050Affiliations:
- Eindhoven University of Technology, Netherlands
- NXP Semiconductors, Eindhoven, The Netherlands
- Philips Research Labs, Eindhoven, Netherlands
- University of Edinburgh, Laboratory for Foundations of Computer Science, UK
According to our database1,
Kees Goossens
authored at least 210 papers
between 1992 and 2024.
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Bibliography
2024
IEEE Des. Test, 2024
2023
Pipelined Architecture for Soft-Decision Iterative Projection Aggregation Decoding for RM Codes.
IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023
Decentralized Configuration of TSCH-Based IoT Networks for Distinctive QoS: A Deep Reinforcement Learning Approach.
IEEE Internet Things J., October, 2023
Proceedings of the IEEE International Conference on Acoustics, 2023
Improved Positioning Precision using a Multi-rate Multi-sensor in Industrial Motion Control Systems.
Proceedings of the European Control Conference, 2023
Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Network, 2023
2022
State-based switching multi-rate controller for improving resource utilization on predictable and composable platforms.
Microprocess. Microsystems, June, 2022
Run-time Per-Class Routing of AVB Flows in In-Vehicle TSN via Composable Delay Analysis.
Proceedings of the 95th IEEE Vehicular Technology Conference, 2022
Proceedings of the IEEE Workshop on Signal Processing Systems, 2022
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022
Proceedings of the 27th IEEE International Conference on Emerging Technologies and Factory Automation, 2022
2021
Log. Methods Comput. Sci., 2021
Reducing Library Characterization Time for Cell-aware Test while Maintaining Test Quality.
J. Electron. Test., 2021
Run-Time Recovery and Failure Analysis of Time-Triggered Traffic in Time Sensitive Networks.
IEEE Access, 2021
Automotive Architecture Topologies: Analysis for Safety-Critical Autonomous Vehicle Applications.
IEEE Access, 2021
Isolation of redundant and mixed-critical automotive applications: effects on the system architecture.
Proceedings of the 93rd IEEE Vehicular Technology Conference, 2021
Analyzable Publish-Subcribe Communication Through a Wait-Free FIFO Channel for MPSoC Real-Time Applications.
Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021
CompROS: A composable ROS2 based architecture for real-time embedded robotic development.
Proceedings of the IEEE/RSJ International Conference on Intelligent Robots and Systems, 2021
Hardware Implementation of Iterative Projection-Aggregation Decoding of Reed-Muller Codes.
Proceedings of the IEEE International Conference on Acoustics, 2021
A Deployment Framework for Quality-Sensitive Applications in Resource-Constrained Dynamic Environments.
Proceedings of the 24th Euromicro Conference on Digital System Design, 2021
Modeling, implementation, and analysis of XRCE-DDS applications in distributed multi-processor real-time embedded systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
2020
Approximated Pareto Analysis for Fast Optimization of Large IEEE 802.15.4 TSCH Networks.
Proceedings of the 31st IEEE Annual International Symposium on Personal, 2020
Tightening the Mesh Size of the Cell-Aware ATPG Net for Catching All Detectable Weakest Faults.
Proceedings of the IEEE European Test Symposium, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous Vehicles.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2019
Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention.
IEEE Trans. Very Large Scale Integr. Syst., 2019
Comparing Platform-aware Control Design Flows for Composable and Predictable TDM-based Execution Platforms.
ACM Trans. Design Autom. Electr. Syst., 2019
Topology Management and TSCH Scheduling for Low-Latency Convergecast in In-Vehicle WSNs.
IEEE Trans. Ind. Informatics, 2019
Proceedings of the 30th IEEE Annual International Symposium on Personal, 2019
Proceedings of the IEEE Latin American Test Symposium, 2019
Proceedings of the IEEE International Test Conference, 2019
Optimization of Cell-Aware ATPG Results by Manipulating Library Cells' Defect Detection Matrices.
Proceedings of the IEEE International Test Conference in Asia, 2019
Proceedings of the 49th Annual IEEE/IFIP International Conference on Dependable Systems and Networks Workshops, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
Delay-based Design of Feedforward Tracking Control for Predictable Embedded Platforms.
Proceedings of the 2019 American Control Conference, 2019
2018
Dependable Interference-Aware Time-Slotted Channel Hopping for Wireless Sensor Networks.
ACM Trans. Sens. Networks, 2018
Guard-Time Design for Symmetric Synchronization in IEEE 802.15.4 Time-Slotted Channel Hopping.
Proceedings of the 87th IEEE Vehicular Technology Conference, 2018
Proceedings of the Computer Safety, Reliability, and Security, 2018
Proceedings of the 29th IEEE Annual International Symposium on Personal, 2018
Proceedings of the 26th Euromicro International Conference on Parallel, 2018
Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
2017
Proceedings of the Handbook of Hardware/Software Codesign., 2017
IEEE Trans. Computers, 2017
Microprocess. Microsystems, 2017
An analytical model for interdependent setup/hold-time characterization of flip-flops.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
Efficient synchronization methods for LET-based applications on a Multi-Processor System on Chip.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017
2016
Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Computers, 2016
Real Time Syst., 2016
Int. J. Online Eng., 2016
Comput. Electr. Eng., 2016
Modeling and Verification of Dynamic Command Scheduling for Real-Time Memory Controllers.
Proceedings of the 2016 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2016
An Experimental Study of Cross-Technology Interference in In-Vehicle Wireless Sensor Networks.
Proceedings of the 19th ACM International Conference on Modeling, 2016
Proceedings of the 5th Mediterranean Conference on Embedded Computing, 2016
Proceedings of the 2016 Workshop on Embedded and Cyber-Physical Systems Education, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
2015
Maximizing the Number of Good Dies for Streaming Applications in NoC-Based MPSoCs Under Process Variation.
ACM Trans. Embed. Comput. Syst., 2015
A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels.
ACM Trans. Embed. Comput. Syst., 2015
Composable and predictable dynamic loading for time-critical partitioned systems on multiprocessor architectures.
Microprocess. Microsystems, 2015
J. Syst. Archit., 2015
Dataflow formalisation of real-time streaming applications on a Composable and Predictable Multi-Processor SOC.
J. Syst. Archit., 2015
Designing applications for heterogeneous many-core architectures with the FlexTiles Platform.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Enhanced Time-Slotted Channel Hopping in WSNs Using Non-intrusive Channel-Quality Estimation.
Proceedings of the 12th IEEE International Conference on Mobile Ad Hoc and Sensor Systems, 2015
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015
Proceedings of the 2015 International Conference on Embedded Software, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015
A generic, scalable and globally arbitrated memory tree for shared DRAM access in real-time systems.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
2014
Process-variation-aware mapping of best-effort and real-time streaming applications to MPSoCs.
ACM Trans. Embed. Comput. Syst., 2014
IEEE Trans. Computers, 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 26th Euromicro Conference on Real-Time Systems, 2014
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Coupling TDM NoC and DRAM controller for cost and performance optimization of real-time systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Exploiting expendable process-margins in DRAMs for run-time performance optimization.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
2013
Virtual execution platforms for mixed-time-criticality systems: the CompSOC architecture and design flow.
SIGBED Rev., 2013
Parallel Comput., 2013
TeMNOT: A test methodology for the non-intrusive online testing of FPGA with hardwired network on chip.
Microprocess. Microsystems, 2013
A unified execution model for multiple computation models of streaming applications on a composable MPSoC.
J. Syst. Archit., 2013
Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors.
Proceedings of the 28th Annual ACM Symposium on Applied Computing, 2013
A software-based technique enabling composable hierarchical preemptive scheduling for time-triggered applications.
Proceedings of the 2013 IEEE 19th International Conference on Embedded and Real-Time Computing Systems and Applications, 2013
Proceedings of the 10th FPGAworld Conference, 2013
Throughput analysis and Voltage-Frequency Island partitioning for streaming applications under process variation.
Proceedings of the 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
Architecture and optimal configuration of a real-time multi-channel memory controller.
Proceedings of the Design, Automation and Test in Europe, 2013
System and circuit level power modeling of energy-efficient 3D-stacked wide I/O DRAMs.
Proceedings of the Design, Automation and Test in Europe, 2013
Towards variation-aware system-level power estimation of DRAMs: an empirical approach.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013
2012
Customisation of on-chip network interconnects and experiments in field-programmable gate arrays.
IET Comput. Digit. Tech., 2012
Comparative analysis of soft and hard on-chip interconnects for field-programmable gate arrays.
IET Comput. Digit. Tech., 2012
Decoupled inter- and intra-application scheduling for composable and robust embedded MPSoC platforms.
Proceedings of the Workshop on Software and Compilers for Embedded Systems, 2012
Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures.
Proceedings of the 2012 International Conference on Embedded Computer Systems: Architectures, 2012
Hardware design and implementation of a Network-on-Chip based load balancing switch fabric.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012
Process-variation aware mapping of real-time streaming applications to MPSoCs for improved yield.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the 30th International IEEE Conference on Computer Design, 2012
Proceedings of the 2012 Interconnection Network Architecture, 2012
Embedded computer architecture laboratory: a hands-on experience programming embedded systems with resource and energy constraints.
Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, 2012
Proceedings of the IEEE 10th Symposium on Embedded Systems for Real-time Multimedia, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012
Proceedings of the 49th Annual Design Automation Conference 2012, 2012
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012
2011
Microprocess. Microsystems, 2011
Microprocess. Microsystems, 2011
A quantitative evaluation of a Network on Chip design flow for multi-core consumer multimedia applications.
Des. Autom. Embed. Syst., 2011
Des. Autom. Embed. Syst., 2011
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011
Resource-Efficient Real-Time Scheduling Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011
Proceedings of the 17th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2011
Enhancing the security of time-division-multiplexing networks-on-chip through the use of multipath routing.
Proceedings of the 4th International Workshop on Network on Chip Architectures, 2011
Proceedings of the Fifth International Workshop on Interconnection Network Architecture, 2011
Proceedings of the 11th International Conference on Embedded Software, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
PUMA: Placement Unification with Mapping and Guaranteed Throughput Allocation on an FPGA Using a Hardwired NoC.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the Design, Automation and Test in Europe, 2011
An FPGA bridge preserving traffic quality of service for on-chip network-based systems.
Proceedings of the Design, Automation and Test in Europe, 2011
Architectures and modeling of predictable memory controllers for improved system integration.
Proceedings of the Design, Automation and Test in Europe, 2011
Memory controllers for high-performance and real-time MPSoCs: requirements, architectures, and future trends.
Proceedings of the 9th International Conference on Hardware/Software Codesign and System Synthesis, 2011
Proceedings of the 8th Conference on Computing Frontiers, 2011
Composability and Predictability for Independent Application Development, Verification, and Execution.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011
2010
J. Electron. Test., 2010
On-chip network interfaces supporting automatic burst write creation, posted writes and read prefetch.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010
Proceedings of the 16th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2010
Obtaining consistent global state dumps to interactively debug systems on chip with multiple clocks.
Proceedings of the IEEE International High Level Design Validation and Test Workshop, 2010
Proceedings of the 15th European Test Symposium, 2010
Proceedings of the 8th IEEE Workshop on Embedded Systems for Real-Time Multimedia, 2010
Composable Dynamic Voltage and Frequency Scaling and Power Management for Dataflow Applications.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
The aethereal network on chip after ten years: goals, evolution, lessons, and future.
Proceedings of the 47th Design Automation Conference, 2010
Proceedings of the 8th Annual Conference on Communication Networks and Services Research, 2010
2009
ACM Trans. Design Autom. Electr. Syst., 2009
Enabling application-level performance guarantees in network-based systems on chip by applying dataflow analysis.
IET Comput. Digit. Tech., 2009
Efficient Service Allocation in Hardware Using Credit-Controlled Static-Priority Arbitration.
Proceedings of the 15th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, 2009
Composable and Persistent-State Application Swapping on FPGAs Using Hardwired Network on Chip.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
Proceedings of the Global Communications Conference, 2009. GLOBECOM 2009, Honolulu, Hawaii, USA, 30 November, 2009
Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models.
Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, 2009
2008
Proceedings of the Fourteenth IEEE Internationl Conference on Embedded and Real-Time Computing Systems and Applications, 2008
Debugging Distributed-Shared-Memory Communication at Multiple Granularities in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Applying Dataflow Analysis to Dimension Buffers for Guaranteed Performance in Networks on Chip.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.
Proceedings of the Second International Symposium on Networks-on-Chips, 2008
Impact of power-management granularity on the energy-quality trade-off for soft and hard real-time applications.
Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2008
Proceedings of the 13th European Test Symposium, 2008
Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis, 2008
2007
A Unified Approach to Mapping and Routing on a Network-on-Chip for Both Best-Effort and Guaranteed Service Traffic.
VLSI Design, 2007
VLSI Design, 2007
Wrapper design for the reuse of a bus, network-on-chip, or other functional interconnect as test access mechanism.
IET Comput. Digit. Tech., 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the First International Symposium on Networks-on-Chips, 2007
Proceedings of the 12th European Test Symposium, 2007
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip.
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007
2006
Comparison of an Æthereal Network on Chip and Traditional Interconnects - Two Case Studies.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006
Comparison of An Æthereal Network on Chip and A Traditional Interconnect for A Multi-Processor DVB-T System on Chip.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the International Symposium on Industrial Embedded Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 11th European Test Symposium, 2006
Proceedings of the Conference on Design, Automation and Test in Europe: Designers' Forum, 2006
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.
Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
ACM Trans. Design Autom. Electr. Syst., 2005
An efficient on-chip NI offering guaranteed services, shared-memory abstraction, and flexible network configuration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005
IEEE Des. Test Comput., 2005
A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification.
Proceedings of the 2005 Design, 2005
A unified approach to constrained mapping and routing on network-on-chip architectures.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005
Proceedings of the Correct Hardware Design and Verification Methods, 2005
Proceedings of the Fifth International Conference on Application of Concurrency to System Design (ACSD 2005), 2005
2004
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004
An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
2003
IEEE Commun. Mag., 2003
Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip.
Proceedings of the 2003 Design, 2003
Proceedings of the Networks on Chip, 2003
2002
C-HEAP: A Heterogeneous Multi-Processor Architecture Template and Scalable and Flexible Protocol for the Design of Embedded Signal Processing Systems.
Des. Autom. Embed. Syst., 2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
Proceedings of the 2002 Design, 2002
Proceedings of the Coordination Models and Languages, 5th International Conference, 2002
2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
1998
Proceedings of the 1998 International Symposium on Low Power Electronics and Design, 1998
1995
Proceedings of the Correct Hardware Design and Verification Methods, 1995
1993
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1993
Embedding hardware description languages in proof systems.
PhD thesis, 1993
1992
Operational Semantics Based on Formal Symbolic Simulation.
Proceedings of the Higher Order Logic Theorem Proving and its Applications, 1992