Albert van der Werf

Affiliations:
  • Philips Research Laboratories, Eindhoven, The Netherlands
  • Eindhoven University of Technology, The Netherlands (PhD 1989)
  • University of Twente, The Netherlands (PhD 1989)


According to our database1, Albert van der Werf authored at least 23 papers between 1985 and 2007.

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Bibliography

2007
Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2007

2001
Synthesizing A Long Latency Unit Within Vliw Processor.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

HW-SW Co-Design and Verification of a Multi-Standard Video and Image Codec.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Power-efficient layered turbo decoder processor.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Functional units with conditional input/output behavior in VLIW processors.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Mapping Array Communication onto FIFO Communication - Towards an Implementation.
Proceedings of the 13th International Symposium on System Synthesis, 2000

Scheduling Coarse-Grain Operations for VLIW Processors.
Proceedings of the 13th International Symposium on System Synthesis, 2000

1998
The Complexity of Multidimensional Periodic Scheduling.
Discret. Appl. Math., 1998

1997
Mpeg2 Video Encoding in Consumer Electronics.
J. VLSI Signal Process., 1997

I.McIC: a single-chip MPEG-2 video encoder for storage.
IEEE J. Solid State Circuits, 1997

1996
The complexity of generalized retiming problems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Multidimensional Periodic Scheduling Model and Complexity.
Proceedings of the Euro-Par '96 Parallel Processing, 1996

1995
PHIDEO: High-level synthesis for high throughput applications.
J. VLSI Signal Process., 1995

Improved force-directed scheduling in high-throughput digital signal processing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

1994
Efficient timing constraint derivation for optimal retiming high speed processing units.
Proceedings of the 7th International Symposium on High Level Synthesis, 1994

1993
Architectural strategies for high-throughput applications.
J. VLSI Signal Process., 1993

A new method for retiming multi-functional processing units.
Proceedings of the VLSI 93, 1993

Allocation of multiport memories for hierarchical data stream.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Area optimization of multi-functional processing units.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

Efficiency improvements for force-directed scheduling.
Proceedings of the 1992 IEEE/ACM International Conference on Computer-Aided Design, 1992

1991
Hierarchical Retiming Including Pipelining.
Proceedings of the VLSI 91, 1991

PHIDEO: a silicon compiler for high speed algorithms.
Proceedings of the conference on European design automation, 1991

1985
MOD/R : A knowledge assisted approach towards top-down only CMOS VLSI design.
Microprocessing and Microprogramming, 1985


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