Bart Mesman

According to our database1, Bart Mesman authored at least 50 papers between 1997 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
The neuro vector engine: Flexibility to improve convolutional net efficiency for wearable vision.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
VLIW Code Generation for a Convolutional Network Accelerator.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Inter-tile reuse optimization applied to bandwidth constrained embedded accelerators.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2013
Memory-centric accelerator design for Convolutional Neural Networks.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012
GPU-Vote: A Framework for Accelerating Voting Algorithms on GPU.
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012

Scheduling for register file energy minimization in explicit datapath architectures.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Distributed resource management for concurrent execution of multimedia applications on MPSoC platforms.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Skeleton-based automatic parallelization of image processing algorithms for GPUs.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

MOVE-Pro: A low power and high code density TTA architecture.
Proceedings of the 2011 International Conference on Embedded Computer Systems: Architectures, 2011

Bottlenecks and Tradeoffs in High Frame Rate Visual Servoing: A Case Study.
Proceedings of the IAPR Conference on Machine Vision Applications (IAPR MVA 2011), 2011

Demo: An embedded vision system for high frame rate visual servoing.
Proceedings of the 2011 Fifth ACM/IEEE International Conference on Distributed Smart Cameras, 2011

An MPSoC design approach for multiple use-cases of throughput constrainted applications.
Proceedings of the 8th Conference on Computing Frontiers, 2011

High performance predictable histogramming on GPUs: exploring and evaluating algorithm trade-offs.
Proceedings of 4th Workshop on General Purpose Processing on Graphics Processing Units, 2011

Efficiency Optimization of Trainable Feature Extractors for a Consumer Platform.
Proceedings of the Advances Concepts for Intelligent Vision Systems, 2011

Feasibility Analysis of Ultra High Frame Rate Visual Servoing on FPGA and SIMD Processor.
Proceedings of the Advances Concepts for Intelligent Vision Systems, 2011

Fast Hough Transform on GPUs: Exploration of Algorithm Trade-Offs.
Proceedings of the Advances Concepts for Intelligent Vision Systems, 2011

2010
Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications.
Journal of Systems Architecture - Embedded Systems Design, 2010

Fast Huffman decoding by exploiting data level parallelism.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

Compile-time GPU memory access optimizations.
Proceedings of the 2010 International Conference on Embedded Computer Systems: Architectures, 2010

A predictable communication assist.
Proceedings of the 7th Conference on Computing Frontiers, 2010

2009
Performance evaluation of concurrently executing parallel applications on multi-processor systems.
Proceedings of the 2009 International Conference on Embedded Computer Systems: Architectures, 2009

2008
Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA.
ACM Trans. Design Autom. Electr. Syst., 2008

Analyzing composability of applications on MPSoC platforms.
Journal of Systems Architecture - Embedded Systems Design, 2008

DC-SIMD : Dynamic communication for SIMD processors.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

Enabling MPSoC Design Space Exploration on FPGAs.
Proceedings of the Wireless Networks, 2008

Real-Time Hough Transform on 1-D SIMD Processors: Implementation and Architecture Exploration.
Proceedings of the Advanced Concepts for Intelligent Vision Systems, 2008

2007
Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA.
Proceedings of the FPL 2007, 2007

A Probabilistic Approach to Model Resource Contention for Performance Estimation of Multi-featured Media Devices.
Proceedings of the 44th Design Automation Conference, 2007

2006
RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications.
J. Embedded Computing, 2006

Run-time reconfiguration of communication in SIMD architectures.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Resource Manager for Non-preemptive Heterogeneous Multiprocessor System-on-chip.
Proceedings of the 2006 4th Workshop on Embedded Systems for Real-Time Multimedia, 2006

Global Analysis of Resource Arbitration for MPSoC.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Dynamic-SIMD for lens distortion compensation.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
Predictable Embedding of Large Data Structures in Multiprocessor Networks-on-Chip.
Proceedings of the 2005 Design, 2005

2004
Predictable Embedded Multiprocessor System Design.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004

2003
Static resource models for code-size efficient embedded processors.
ACM Trans. Embedded Comput. Syst., 2003

Reconfigurable Instruction-Set Application-Tuning for DSP.
Journal of Circuits, Systems, and Computers, 2003

Limited Address Range Architecture for Reducing Code Size in Embedded Processors.
Proceedings of the Software and Compilers for Embedded Systems, 7th International Workshop, 2003

Task-level timing models for guaranteed performance in multiprocessor networks-on-chip.
Proceedings of the International Conference on Compilers, 2003

2002
Practical Instruction Set Design and Compiler Retargetability Using Static Resource Models.
Proceedings of the 2002 Design, 2002

2001
Static resource models of instruction sets.
Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Constraint Satisfaction for Relative Location Assignment and Scheduling.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Constraint satisfaction for storage files with Fifos or stacks during scheduling.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Constraint analysis for code generation: basic techniques and applications in FACTS.
ACM Trans. Design Autom. Electr. Syst., 2000

1999
Constraint analysis for DSP code generation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Efficient Scheduling of DSP Code on Processors with Distributed Register Files.
Proceedings of the 12th International Symposium on System Synthesis, 1999

Identification and Exploitation of Symmetries in DSP Algorithms.
Proceedings of the 1999 Design, 1999

1998
A Constraint Driven Approach to Loop Pipelining and Register Binding.
Proceedings of the 1998 Design, 1998

1997
Constraint Analysis for DSP Code Generation.
Proceedings of the 10th International Symposium on System Synthesis, 1997


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