Navaneeth Kunhi Purayil

According to our database, Navaneeth Kunhi Purayil authored at least 5 papers between 2025 and 2026.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2026

Vmxdotp: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration.

Max Wipfli, Gamze Islamoglu, Navaneeth Kunhi Purayil, Angelo Garofalo, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference, 2026

2025

CMOS 2.0 - Redefining the Future of Scaling.

Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert

CoRR, October, 2025

TROOP: At-the-Roofline Performance for Vector Processors on Low Operational Intensity Workloads.

Navaneeth Kunhi Purayil, Diyou Shen, Matteo Perotti, Luca Benini

Proceedings of the 43rd IEEE International Conference on Computer Design, 2025

Invited Paper: CMOS 2.0 - Redefining the Future of Scaling.

Moritz Brunion, Navaneeth Kunhi Purayil, Francesco Dell'Atti, Sebastian Lam, Refik Bilgic, Mehdi B. Tahoori, Luca Benini, Julien Ryckaert

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025

AraXL: A Physically Scalable, Ultra-Wide RISC-V Vector Processor Design for Fast and Efficient Computation on Long Vectors.

Navaneeth Kunhi Purayil, Matteo Perotti, Tim Fischer, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference, 2025