Julien Ryckaert

According to our database, Julien Ryckaert authored at least 59 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2023

3D SRAM Macro Design in 3D Nanofabric Process Technology.

Dawit Burusie Abdi, Shairfe Muhammad Salahuddin, Jürgen Bömmels, Edouard Giacomin, Pieter Weckx, Julien Ryckaert, Geert Hellings, Francky Catthoor

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2023

PPA and Scaling Potential of Backside Power Options in N2 and A14 Nanosheet Technology.

S. Yang, Pieter Schuddinck, Marie Garcia Bardon, Yang Xiang, Anabela Veloso, B. T. Chan, Gioele Mirabelli, Gaspard Hiblot, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Block-level Evaluation and Optimization of Backside PDN for High-Performance Computing at the A14 node.

Giuliano Sisto, R. Preston, Rongmei Chen, Gioele Mirabelli, Anita Farokhnejad, Yun Zhou, Ivan Ciofi, Anne Jourdain, A. Veloso, Michele Stucchi, Odysseas Zografos, Pieter Weckx, Geert Hellings, Julien Ryckaert

Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023

Impact of interconnects enhancement on SRAM design beyond 5nm technology node.

Mohit Kumar Gupta, Pieter Weckx, Manu Perumkunnil Komalan, Julien Ryckaert

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Design Technology co-optimization of 1D-1VCMA to improve read performance for SCM applications.

Mohit Kumar Gupta, Manu Perumkunnil, Dwaipayan Biswas, Saeideh Alinezhad Chamazcoti, Gouri Sankar Kar, Arnaud Furnémont, Julien Ryckaert

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

Towards Chip-Package-System Co-optimization of Thermally-limited System-On-Chips (SOCs).

Subrat Mishra, Sankatali Venkateswarlu, Bjorn Vermeersch, Moritz Brunion, Melina Lofrano, Dawit Burusie Abdi, Herman Oprins, Dwaipayan Biswas, Odysseas Zografos, Gaspard Hiblot, Geert Van der Plas, Pieter Weckx, Geert Hellings, James Myers, Francky Catthoor, Julien Ryckaert

Proceedings of the IEEE International Reliability Physics Symposium, 2023

MNEMOSENE++: Scalable Multi-Tile Design with Enhanced Buffering and VGSOT-MRAM based Compute-in-Memory Crossbar Array.

Carlos Escuin, Fernando García-Redondo, Mahdi Zahedi, Pablo Ibáñez, Teresa Monreal, Víctor Viñals, José María Llabería, James Myers, Julien Ryckaert, Dwaipayan Biswas, Francky Catthoor

Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023

2022

Evaluation of Nanosheet and Forksheet Width Modulation for Digital IC Design in the Sub-3-nm Era.

Giuliano Sisto, Odysseas Zografos, Bilal Chehab, Naveen Kakarla, Yang Xiang, Dragomir Milojevic, Pieter Weckx, Geert Hellings, Julien Ryckaert

IEEE Trans. Very Large Scale Integr. Syst., 2022

Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.

Bjorn Vermeersch, Erik Bury, Yang Xiang, Pieter Schuddinck, Krishna K. Bhuwalka, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails.

Anabela Veloso, Anne Jourdain, D. Radisic, Rongmei Chen, G. Arutchelvan, B. O'Sullivan, Hiroaki Arimura, Michele Stucchi, An De Keersgieter, M. Hosseini, T. Hopf, K. D'Have, S. Wang, E. Dupuy, G. Mannaert, Kevin Vandersmissen, S. Iacovo, P. Marien, S. Choudhury, F. Schleicher, F. Sebaai, Y. Oniki, X. Zhou, A. Gupta, Tom Schram, B. Briggs, C. Lorant, E. Rosseel, Andriy Hikavyy, Roger Loo, J. Geypen, D. Batuk, G. T. Martinez, J. P. Soulie, Katia Devriendt, B. T. Chan, S. Demuynck, Gaspard Hiblot, Geert Van der Plas, Julien Ryckaert, Gerald Beyer, E. Dentoni Litta, Eric Beyne, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.

Kateryna Serbulova, S.-H. Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Dimitri Linten, J. De Boeck, Guido Groeseneken, Julien Ryckaert, Geert Van der Plas, Eric Beyne, Eugenio Dentoni Litta, Naoto Horiguchi

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.

Pieter Schuddinck, Fabian M. Bufler, Yang Xiang, Anita Farokhnejad, Gioele Mirabelli, Anne Vandooren, Bilal Chehab, A. Gupta, César Roda Neve, Geert Hellings, Julien Ryckaert

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.

Rongmei Chen, Giuliano Sisto, Michele Stucchi, Anne Jourdain, Kenichi Miyaguchi, Pieter Schuddinck, P. Woeltgens, H. Lin, Naveen Kakarla, Anabela Veloso, Dragomir Milojevic, Odysseas Zografos, Pieter Weckx, Geert Hellings, Geert Van der Plas, Julien Ryckaert, Eric Beyne

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design enablement of CFET devices for sub-2nm CMOS nodes.

Odysseas Zografos, Bilal Chehab, Pieter Schuddinck, Gioele Mirabelli, Naveen Kakarla, Yang Xiang, Pieter Weckx, Julien Ryckaert

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021

Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks.

Amita Rawat, Krishna K. Bhuwalka, Philippe Matagne, Bjorn Vermeersch, Hao Wu, Geert Hellings, Julien Ryckaert, Changze Liu

Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020

Heterogeneous 3D Integration for a RISC-V System With STT-MRAM.

Lingjun Zhu, Lennart Bamberg, Anthony Agnesina, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Julien Ryckaert, Alberto García-Ortiz, Sung Kyu Lim

IEEE Comput. Archit. Lett., 2020

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.

Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon

Proceedings of the VLSI-SoC: Design Trends, 2020

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.

Edouard Giacomin, Jürgen Bömmels, Julien Ryckaert, Francky Catthoor, Pierre-Emmanuel Gaillardon

Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Device Scaling roadmap and its implications for Logic and Analog platform.

Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert

Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2019

Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.

Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017

Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.

Trong Huynh Bao, Julien Ryckaert, Zsolt Tokei, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq

IEEE Trans. Very Large Scale Integr. Syst., 2017

SRAM designs for 5nm node and beyond: Opportunities and challenges.

Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2016

Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue.

Julien Ryckaert

Proceedings of the 2016 on International Symposium on Physical Design, 2016

2015

Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.

Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Dmitry Yakimets, Abdelkarim Mercha, Diederik Verkest, Aaron Voon-Yew Thean, Piet Wambacq

Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of interconnect multiple-patterning variability on SRAMs.

Ioannis Karageorgos, Michele Stucchi, Praveen Raghavan, Julien Ryckaert, Zsolt Tokei, Diederik Verkest, Rogier Baert, Sushil Sakhare, Wim Dehaene

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Holisitic device exploration for 7nm node.

Praveen Raghavan, Marie Garcia Bardon, Doyoung Jang, P. Schuddinck, Dmitry Yakimets, Julien Ryckaert, Abdelkarim Mercha, Naoto Horiguchi, Nadine Collaert, Anda Mocuta, Dan Mocuta, Zsolt Tokei, Diederik Verkest, Aaron Thean, An Steegen

Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014

Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.

Trong Huynh Bao, Dmitry Yakimets, Julien Ryckaert, Ivan Ciofi, Rogier Baert, Anabela Veloso, Jürgen Bömmels, Nadine Collaert, Philippe Roussel, S. Demuynck, Praveen Raghavan, Abdelkarim Mercha, Zsolt Tokei, Diederik Verkest, Aaron Thean, Piet Wambacq

Proceedings of the 44th European Solid State Device Research Conference, 2014

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy.

Santhosh Kumar Rethinagiri, Oscar Palomar, Anita Sobe, Thomas Knauth, Wojciech M. Barczynski, Gulay Yalcin, Yarco Hayduk, Adrián Cristal, Osman S. Unsal, Pascal Felber, Christof Fetzer, Julien Ryckaert, Gina Alioto

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Design Technology co-optimization for N10.

Julien Ryckaert, Praveen Raghavan, Rogier Baert, Marie Garcia Bardon, Mircea Dusa, Arindam Mallik, Sushil Sakhare, Boris Vandewalle, Piet Wambacq, Bharani Chava, Kris Croes, Morin Dehan, Doyoung Jang, Philippe Leray, Tsung-Te Liu, Kenichi Miyaguchi, Bertrand Parvais, Pieter Schuddinck, Philippe Weemaes, Abdelkarim Mercha, Jürgen Bömmels, Naoto Horiguchi, Greg McIntyre, Aaron Thean, Zsolt Tökei, Shaunee Cheng, Diederik Verkest, An Steegen

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014

2013

Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter.

Michal Rakowski, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Bradley Snyder, Peter O'Brien, Julien Ryckaert, Philippe Absil, Joris Van Campenhout

Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.

Arindam Mallik, Paul Zuber, Tsung-Te Liu, Bharani Chava, Bhavana Ballal, Pablo Royer Del Bario, Rogier Baert, Kris Croes, Julien Ryckaert, Mustafa Badaroglu, Abdelkarim Mercha, Diederik Verkest

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012

RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.

Ewout Martens, André Bourdoux, Aïssa Couvreur, Robert Fasthuber, Peter Van Wesemael, Geert Van der Plas, Jan Craninckx, Julien Ryckaert

IEEE J. Solid State Circuits, 2012

Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator.

Michal Rakowski, Julien Ryckaert, Marianna Pantouvaki, Hui Yu, Wim Bogaerts, Kristin De Meyer, Michiel Steyaert, Philippe P. Absil, Joris Van Campenhout

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A calibrated pathfinding model for signal integrity analysis on interposer.

Jaemin Kim, Sunyoung Kim, Julien Ryckaert, Mikael Detalle, Nele Van Hoovels, Pol Marchal

Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011

DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.

Dragomir Milojevic, Herman Oprins, Julien Ryckaert, Paul Marchal, Geert Van der Plas

Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010

A 0.5 mm ² Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler.

Arnd Geis, Julien Ryckaert, Lynn Bos, Gerd Vandersteen, Yves Rolain, Jan Craninckx

IEEE J. Solid State Circuits, 2010

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS.

Lynn Bos, Gerd Vandersteen, Pieter Rombouts, Arnd Geis, Alonso Morgado, Yves Rolain, Geert Van der Plas, Julien Ryckaert

IEEE J. Solid State Circuits, 2010

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS.

Alonso Morgado, Rocío del Río, José M. de la Rosa, Lynn Bos, Julien Ryckaert, Geert Van der Plas

Proceedings of the 36th European Solid-State Circuits Conference, 2010

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation.

Arnd Geis, Pierluigi Nuzzo, Julien Ryckaert, Yves Rolain, Gerd Vandersteen, Jan Craninckx

Proceedings of the Design, Automation and Test in Europe, 2010

2009

A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS.

Julien Ryckaert, Jonathan Borremans, Bob Verbruggen, Lynn Bos, Costantino Armiento, Jan Craninckx, Geert Van der Plas

IEEE J. Solid State Circuits, 2009

A 2-mm² 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS.

Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Jonathan Borremans, Joris Van Driessche, Jan Craninckx, Mark Ingels

IEEE J. Solid State Circuits, 2009

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.

Jonathan Borremans, Julien Ryckaert, Claude Desset, Maarten Kuijk, Piet Wambacq, Jan Craninckx

IEEE J. Solid State Circuits, 2009

A 2mm² 0.1-to-5GHz SDR receiver in 45nm digital CMOS.

Vito Giannini, Pierluigi Nuzzo, Charlotte Soens, Kameswaran Vengattaramane, Michiel Steyaert, Julien Ryckaert, Michaël Goffioul, Björn Debaillie, Joris Van Driessche, Jan Craninckx, Mark Ingels

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.

Lynn Bos, Gerd Vandersteen, Julien Ryckaert, Pieter Rombouts, Yves Rolain, Geert Van der Plas

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008

A Low Power, Reconfigurable IR-UWB System.

Marian Verhelst, Julien Ryckaert, Yves Vanderperren, Wim Dehaene

Proceedings of IEEE International Conference on Communications, 2008

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.

Jonathan Borremans, Julien Ryckaert, Piet Wambacq, Maarten Kuijk, Jan Craninckx

Proceedings of the ESSCIRC 2008, 2008

2007

A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.

Julien Ryckaert, Marian Verhelst, Mustafa Badaroglu, Stefano D'Amico, Vincent De Heyn, Claude Desset, Pierluigi Nuzzo, Bart van Poucke, Piet Wambacq, Andrea Baschirotto, Wim Dehaene, Geert Van der Plas

IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.

Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Bart van Poucke, Jan Craninckx

IEEE J. Solid State Circuits, 2007

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers.

Claude Desset, Mustafa Badaroglu, Julien Ryckaert, Bart van Poucke

Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a.

Julien Ryckaert, Geert Van der Plas, Vincent De Heyn, Claude Desset, Geert Vanwijnsberghe, Bart van Poucke, Jan Craninckx

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.

Vincent De Heyn, Geert Van der Plas, Julien Ryckaert, Jan Craninckx

Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006

Ultra-wideband channel model for communication around the human body.

Andrew Fort, Julien Ryckaert, Claude Desset, Philippe De Doncker, Piet Wambacq, Leo Van Biesen

IEEE J. Sel. Areas Commun., 2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.

Mustafa Badaroglu, Claude Desset, Julien Ryckaert, Vincent De Heyn, Geert Van der Plas, Piet Wambacq, Bart van Poucke

EURASIP J. Wirel. Commun. Netw., 2006

Human++: Emerging Technology for Body Area Networks.

Julien Penders, Bert Gyselinckx, Ruud J. M. Vullers, Olivier Rousseaux, Mladen Berekovic, Michael De Nil, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Human++: Emerging Technology for Body Area Networks.

Bert Gyselinckx, Ruud J. M. Vullers, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov

Proceedings of the IFIP VLSI-SoC 2006, 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.

Julien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, Hans Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005

Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.

Julien Ryckaert, Claude Desset, Andrew Fort, Mustafa Badaroglu, Vincent De Heyn, Piet Wambacq, Geert Van der Plas, Stéphane Donnay, Bart van Poucke, Bert Gyselinckx

IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Ultra wide-band body area channel model.

Andrew Fort, Claude Desset, Julien Ryckaert, Philippe De Doncker, Leo Van Biesen, Stéphane Donnay

Proceedings of IEEE International Conference on Communications, 2005

Human++: autonomous wireless sensors for body area networks.

Bert Gyselinckx, Chris Van Hoof, Julien Ryckaert, Refet Firat Yazicioglu, Paolo Fiorini, Vladimir Leonov

Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005