Julien Ryckaert

According to our database1, Julien Ryckaert authored at least 51 papers between 2005 and 2022.

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Bibliography

2022
Self-Heating in iN8-iN2 CMOS Logic Cells: Thermal Impact of Architecture (FinFET, Nanosheet, Forksheet and CFET) and Scaling Boosters.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

PPAC of sheet-based CFET configurations for 4 track design with 16nm metal pitch.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Backside PDN and 2.5D MIMCAP to Double Boost 2D and 3D ICs IR-Drop beyond 2nm Node.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

Design enablement of CFET devices for sub-2nm CMOS nodes.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Performance Trade-Off Scenarios for GAA Nanosheet FETs Considering Inner-spacers and Epi-induced Stress: Understanding & Mitigating Process Risks.
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021

2020
Heterogeneous 3D Integration for a RISC-V System With STT-MRAM.
IEEE Comput. Archit. Lett., 2020

3D Nanofabric: Layout Challenges and Solutions for Ultra-scaled Logic Designs.
Proceedings of the VLSI-SoC: Design Trends, 2020

Layout Considerations of Logic Designs Using an N-layer 3D Nanofabric Process Flow.
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020

Device Scaling roadmap and its implications for Logic and Analog platform.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2020

2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017

SRAM designs for 5nm node and beyond: Opportunities and challenges.
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

2016
Scaling Beyond 7nm: Design-Technology Co-optimization at the Rescue.
Proceedings of the 2016 on International Symposium on Physical Design, 2016

2015
Design technology co-optimization for enabling 5nm gate-all-around nanowire 6T SRAM.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Impact of interconnect multiple-patterning variability on SRAMs.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Holisitic device exploration for 7nm node.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014


2013
Low-power, low-penalty, flip-chip integrated, 10Gb/s ring-based 1V CMOS photonics transmitter.
Proceedings of the 2013 Optical Fiber Communication Conference and Exposition and the National Fiber Optic Engineers Conference (OFC/NFOEC), 2013

TEASE: a systematic analysis framework for early evaluation of FinFET-based advanced technology nodes.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
RF-to-Baseband Digitization in 40 nm CMOS With RF Bandpass ΔΣ Modulator and Polyphase Decimation Filter.
IEEE J. Solid State Circuits, 2012

Low-Power, 10-Gbps 1.5-Vpp differential CMOS driver for a silicon electro-optic ring modulator.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A calibrated pathfinding model for signal integrity analysis on interposer.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

2011
DRAM-on-logic Stack - Calibrated thermal and mechanical models integrated into PathFinding flow.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 0.5 mm <sup>2</sup> Power-Scalable 0.5-3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler.
IEEE J. Solid State Circuits, 2010

Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM/Bluetooth/UMTS.
IEEE J. Solid State Circuits, 2010

A 100kHz-10MHz BW, 78-to-52dB DR, 4.6-to-11mW flexible SC ΣΔ modulator in 1.2-V 90-nm CMOS.
Proceedings of the 36th European Solid-State Circuits Conference, 2010

An 11.6-19.3mW 0.375-13.6GHz CMOS frequency synthesizer with rail-to-rail operation.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
A 2.4 GHz Low-Power Sixth-Order RF Bandpass ΔΣ Converter in CMOS.
IEEE J. Solid State Circuits, 2009

A 2-mm<sup>2</sup> 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS.
IEEE J. Solid State Circuits, 2009

A 2mm<sup>2</sup> 0.1-to-5GHz SDR receiver in 45nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A multirate 3.4-to-6.8mW 85-to-66dB DR GSM/bluetooth/UMTS cascade DT ΔΣM in 90nm digital CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2008
A Low Power, Reconfigurable IR-UWB System.
Proceedings of IEEE International Conference on Communications, 2008

A low-complexity, low phase noise, low-voltage phase-aligned ring oscillator in 90 nm digital CMOS.
Proceedings of the ESSCIRC 2008, 2008

2007
A CMOS Ultra-Wideband Receiver for Low Data-Rate Communication.
IEEE J. Solid State Circuits, 2007

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a.
IEEE J. Solid State Circuits, 2007

Optimized Signal Acquisition for Low-Complexity and Low-Power IR-UWB Transceivers.
Proceedings of the 65th IEEE Vehicular Technology Conference, 2007

A 0.65-to-1.4nJ/burst 3-to-10GHz UWB Digital TX in 90nm CMOS for IEEE 802.15.4a.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A fast start-up 3GHz-10GHz digitally controlled oscillator for UWB impulse radio in 90nm CMOS.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
Ultra-wideband channel model for communication around the human body.
IEEE J. Sel. Areas Commun., 2006

Analog-Digital Partitioning for Low-Power UWB Impulse Radios under CMOS Scaling.
EURASIP J. Wirel. Commun. Netw., 2006

Human++: Emerging Technology for Body Area Networks.
Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Human++: Emerging Technology for Body Area Networks.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2005
Ultra-wide-band transmitter for low-power wireless body area networks: design and evaluation.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005

Ultra wide-band body area channel model.
Proceedings of IEEE International Conference on Communications, 2005

Human++: autonomous wireless sensors for body area networks.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005


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