Matteo Perotti

According to our database, Matteo Perotti authored at least 14 papers between 2021 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

MX: Enhancing RISC-V's Vector ISA for Ultra-Low Overhead, Energy-Efficient Matrix Multiplication.

Matteo Perotti, Yichao Zhang, Matheus A. Cavalcante, Enis Mustafa, Luca Benini

CoRR, 2024

2023

Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS.

Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Near-Memory Parallel Indexing and Coalescing: Enabling Highly Efficient Indirect Access for SpMV.

Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini

CoRR, 2023

Stella Nera: Achieving 161 TOp/s/W with Multiplier-free DNN Acceleration based on Approximate Matrix Multiplication.

Jannis Schönleber, Lukas Cavigelli, Renzo Andri, Matteo Perotti, Luca Benini

CoRR, 2023

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV1.0 Compliant Open-Source Processor.

Matteo Perotti, Matheus A. Cavalcante, Renzo Andri, Lukas Cavigelli, Luca Benini

CoRR, 2023

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency.

Matheus A. Cavalcante, Matteo Perotti, Samuel Riedel, Luca Benini

CoRR, 2023

DARKSIDE: A Heterogeneous RISC-V Compute Cluster for Extreme-Edge On-Chip DNN Inference and Training.

Angelo Garofalo, Yvan Tortorella, Matteo Perotti, Luca Valente, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

CoRR, 2023

Quark: An Integer RISC-V Vector Processor for Sub-Byte Quantized DNN Inference.

MohammadHossein AskariHemmat, Théo Dupuis, Yoan Fournier, Nizar El Zarif, Matheus A. Cavalcante, Matteo Perotti, Frank K. Gürkaynak, Luca Benini, François Leduc-Primeau, Yvon Savaria, Jean-Pierre David

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular Workloads.

Chi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Spatz: A Compact Vector Processing Unit for High-Performance and Energy-Efficient Shared-L1 Clusters.

Matheus A. Cavalcante, Domenic Wüthrich, Matteo Perotti, Samuel Riedel, Luca Benini

Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Darkside: 2.6GFLOPS, 8.7mW Heterogeneous RISC-V Cluster for Extreme-Edge On-Chip DNN Inference and Training.

Angelo Garofalo, Matteo Perotti, Luca Valente, Yvan Tortorella, Alessandro Nadalini, Luca Benini, Davide Rossi, Francesco Conti

Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design.

Matteo Perotti, Matheus A. Cavalcante, Nils Wistoff, Renzo Andri, Lukas Cavigelli, Luca Benini

Proceedings of the 33rd IEEE International Conference on Application-specific Systems, 2022

2021

RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.

Matteo Perotti, Giuseppe Tagliavini, Stefan Mach, Luca Bertaccini, Luca Benini

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Tiny-FPU: Low-Cost Floating-Point Support for Small RISC-V MCU Cores.

Luca Bertaccini, Matteo Perotti, Stefan Mach, Pasquale Davide Schiavone, Florian Zaruba, Luca Benini

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021