Xiaoning Qi

Orcid: 0000-0003-3447-2842

According to our database1, Xiaoning Qi authored at least 12 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Biological knowledge graph-guided investigation of immune therapy response in cancer with graph neural network.
Briefings Bioinform., March, 2023

2020
Xuantie-910: A Commercial Multi-Core 12-Stage Pipeline Out-of-Order 64-bit High Performance RISC-V Processor with Vector Extension : Industrial Product.
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020

Xuantie-910: Innovating Cloud and Edge Computing by RISC-V.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2019
Human trajectory prediction in crowded scene using social-affinity Long Short-Term Memory.
Pattern Recognit., 2019

2007
A New Simulation Method for NBTI Analysis in SPICE Environment.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

2006
Measurement and characterization of pattern dependent process variations of interconnect resistance, capacitance and inductance in nanometer technologies.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

2005
Impact of On-chip Inductance on Power Distribution Network Design for Nanometer Scale Integrated Circuits.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Simulation and analysis of inductive impact on VLSI interconnects in the presence of process variations.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005

2003
A fast simulation approach for inductive effects of VLSI interconnects.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2002
High-frequency characterization of on-chip digital interconnects.
IEEE J. Solid State Circuits, 2002

Accurate Model of Metal-Insulator-Semiconductor Interconnects.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

2000
On-chip inductance modeling and RLC extraction of VLSI interconnects for circuit simulation.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000


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