Roberto Suaya

According to our database, Roberto Suaya authored at least 19 papers between 1990 and 2019.

Collaborative distances:

• Dijkstra number of three.
• Erdős number of three.

2019

Low Power SPI Design Based on Relative Timing Techniques.

Guillermo H. Makar, Francisco J. Badenas, Roberto G. Simone, Alejandro Furfaro, Kenneth S. Stevens, Roberto Suaya

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

2013

Leveraging the geometric properties of on-chip transmission line structures to improve interconnect performance: A case study in 65nm.

Shomit Das, Georgios Manetas, Kenneth S. Stevens, Roberto Suaya

Proceedings of the 2013 Seventh IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2013

2012

Fast High-Frequency Impedance Extraction of Horizontal Interconnects and Inductors in 3-D ICs With Multiple Substrates.

Chuan Xu, Navin Srivastava, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

An efficient framework for passive compact dynamical modeling of multiport linear systems.

Zohaib Mahmood, Roberto Suaya, Luca Daniel

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2010

Corrections to "Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate" [Jul 09 1047-1060].

Navin Srivastava, Chuan Xu, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

Proceedings of the Design, Automation and Test in Europe, 2010

2009

Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a Multilayer Conductive Substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008

High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate.

Navin Srivastava, Roberto Suaya, Kaustav Banerjee

Proceedings of the Design, Automation and Test in Europe, 2008

2007

Efficient implementation of conduction modes for modelling skin effect.

Salvador Ortiz, Roberto Suaya

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Mutual inductance between intentional inductors: closed form expressions.

Rafael Escovar, Salvador Ortiz, Roberto Suaya

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fullwave volumetric Maxwell solver using conduction modes.

Salvador Ortiz, Roberto Suaya

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

2005

An improved long distance treatment for mutual inductance.

Rafael Escovar, Salvador Ortiz, Roberto Suaya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Panel I: who is responsible for the design for manufacturability issues in the era of nano-technologies?

Chung-Kuan Cheng, Steve Lin, Andrew B. Kahng, Keh-Jeng Chang, Vijay Pitchumani, Toshiyuki Shibuya, Roberto Suaya, Zhiping Yu, Fook-Luen Heng, Don MacMillen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004

Optimal design of clock trees for multigigahertz applications.

Rafael Escovar, Roberto Suaya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Mutual inductance extraction and the dipole approximation.

Rafael Escovar, Salvador Ortiz, Roberto Suaya

Proceedings of the 2004 International Symposium on Physical Design, 2004

2002

Transmission line design of clock trees.

Rafael Escovar, Roberto Suaya

Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

1991

A Two-Dimensional Topological Compactor With Octagonal Geometry.

Paul de Dood, John Wawrzynek, Erwin Liu, Roberto Suaya

Proceedings of the 28th Design Automation Conference, 1991

From formal verification to silicon compilation.

Jeffrey Joyce, Erwin Liu, John M. Rushby, Natarajan Shankar, Roberto Suaya, Friedrich W. von Henke

Proceedings of the Compcon Spring '91, San Francisco, 1991

1990

Two-dimensional IC layout compaction based on topological design rule checking.

John Valainis, Sinan Kaptanoglu, Erwin Liu, Roberto Suaya

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990