Nazanin Mansouri

According to our database1, Nazanin Mansouri authored at least 20 papers between 1998 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2009
Power Optimization With Power Islands Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2008
Determining the Optimal Number of Islands in Power Islands Synthesis.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Automated formal verification of scheduling with speculative code motions.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
A high-level register optimization technique for minimizing leakage and dynamic power.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
Power Islands: A High-Level Technique for Counteracting Leakage in Deep Sub-Micron.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.
Proceedings of the Computer and Information Sciences, 2006

Pre-Layout Estimation of Interconnect Lengths for Digital Integrated Circuits.
Proceedings of the 16th International Conference on Electronics, Communications, and Computers (CONIELECOMP 2006), 27 February 2005, 2006

2005
Constraint-based Code mapping for heterogeneous Chip multiprocessors.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

An ILP Formulation for Reliability-Oriented High-Level Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reliability-Centric Hardware/Software Co-Design.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Exploiting PSL standard assertions in a theorem-proving-based verification environment.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Reliability-Centric High-Level Synthesis.
Proceedings of the 2005 Design, 2005

2004
Automated Formal Verification of Scheduling Process Using Finite State Machines with Datapath (FSMD).
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Enhancing scheduling solutions through ant colony optimization.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Exploiting OVL standard assertions in a theorem-proving-based verification environment.
Proceedings of the Second IASTED International Conference on Circuits, 2004

2003
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs.
Proceedings of the International Conference on VLSI, 2003

2000
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs.
Formal Methods Syst. Des., 2000

1999
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.
Proceedings of the 1999 Design, 1999

1998
Automatic data path abstraction for verification of large scale designs.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.
Proceedings of the Formal Methods in Computer-Aided Design, 1998


  Loading...