Suleyman Tosun

Orcid: 0000-0002-3708-2009

According to our database1, Suleyman Tosun authored at least 45 papers between 2003 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
DICEguard: enhancing DICE security for IoT devices with periodic memory forensics.
J. Supercomput., September, 2024

Energy-aware application mapping methods for mesh-based hybrid wireless network-on-chips.
J. Supercomput., July, 2024

2023
Simulated annealing-based high-level synthesis methodology for reliable and energy-aware application specific integrated circuit designs with multiple supply voltages.
Int. J. Circuit Theory Appl., October, 2023

2022
Computation Power and Energy Optimized Task Allocation in Internet of Things.
IEEE Trans. Netw. Serv. Manag., December, 2022

A survey on computation offloading and service placement in fog computing-based IoT.
J. Supercomput., 2022

A High-Level Synthesis Methodology for Energy and Reliability-Oriented Designs.
IEEE Trans. Computers, 2022

Towards QoS-Aware Resource Allocation in Fog Computing: A Theoretical Model.
Proceedings of the International Symposium on Networks, Computers and Communications, 2022

2021
ILP formulation and heuristic method for energy-aware application mapping on 3D-NoCs.
J. Supercomput., 2021

HAFTA: Highly adaptive fault-tolerant routing algorithm for two-dimensional network-on-chips.
Concurr. Comput. Pract. Exp., 2021

Q-Learning-based Routing Algorithm for 3D Network-on-Chips.
Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

2020
Mapping application-specific topology to mesh topology with reconfigurable switches.
IET Comput. Digit. Tech., 2020

Library Characterization of Arithmetic Circuits for Reliability-Aware Designs in SRAM-Based FPGAs.
J. Electron. Test., 2020

2019
Energy-aware and fault-tolerant custom topology design method for network-on-chips.
Nano Commun. Networks, 2019

Genetic Algorithm-based Reliability Optimization for High-Level Synthesis.
J. Circuits Syst. Comput., 2019

Number Analysis and Operator Detection in Telecommunication Systems.
Proceedings of the 2019 International Symposium on Networks, Computers and Communications, 2019

MARM-GA: Mapping Applications to Reconfigurable Mesh using Genetic Algorithm.
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019

2018
Energy-aware partitioning of fault-tolerant irregular topologies for 3D network-on-chips.
J. Supercomput., 2018

Evolutionary task allocation in Internet of Things-based application domains.
Future Gener. Comput. Syst., 2018

2017
Improving combinational circuit resilience against soft errors via selective resource allocation.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Energy-aware application-specific topology generation for 3D Network-on-Chips.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

2016
FPGA implementation of a fault-tolerant application-specific NoC design.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

2015
Application mapping algorithms for mesh-based network-on-chip architectures.
J. Supercomput., 2015

Fault-Tolerant Topology Generation Method for Application-Specific Network-on-Chips.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Energy reduction in 3D NoCs through communication optimization.
Computing, 2015

Moving object detection by a mounted moving camera.
Proceedings of the IEEE EUROCON 2015, 2015

2014
Fault-Tolerant Routing for Irregular-Topology-Based Network-on-Chips.
Proceedings of the Second International Symposium on Computing and Networking, 2014

Fault-Tolerant Irregular Topology Design Method for Network-on-Chips.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

2012
Energy- and reliability-aware task scheduling onto heterogeneous MPSoC architectures.
J. Supercomput., 2012

Application-specific topology generation algorithms for network-on-chip design.
IET Comput. Digit. Tech., 2012

2011
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs.
J. Syst. Archit., 2011

Cluster-based application mapping method for Network-on-Chip.
Adv. Eng. Softw., 2011

2010
FIT: Fast Irregular Topology generation algorithm for application specific NoCs.
IEICE Electron. Express, 2010

2006
Reducing Memory Requirements through Task Recomputation in Embedded Multi-CPU Systems.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

An ILP Formulation for Task Scheduling on Heterogeneous Chip Multiprocessors.
Proceedings of the Computer and Information Sciences, 2006

Multi-Level On-Chip Memory Hierarchy Design for Embedded Chip Multiprocessors.
Proceedings of the 12th International Conference on Parallel and Distributed Systems, 2006

An ILP based approach to address code generation for digital signal processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Using Task Recomputation During Application Mapping in Parallel Embedded Architectures.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

A Novel Essential Prime Implicant Identification Method for Exact Direct Cover Logic Minimization.
Proceedings of the 2006 International Conference on Computer Design & Conference on Computing in Nanotechnology, 2006

2005
Constraint-based Code mapping for heterogeneous Chip multiprocessors.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

On-Chip Memory Management for Embedded MpSoC Architectures Based on Data Compression.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

An ILP Formulation for Reliability-Oriented High-Level Synthesis.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reliability-Centric Hardware/Software Co-Design.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Reliability-Conscious Process Scheduling under Performance Constraints in FPGA-Based Embedded Systems.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Reliability-Centric High-Level Synthesis.
Proceedings of the 2005 Design, 2005

2003
Derving Intermediary RTLs for Verification of Pipelined Synthesized Designs.
Proceedings of the International Conference on VLSI, 2003


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