Viresh Paruthi

According to our database, Viresh Paruthi authored at least 20 papers between 1998 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Chain-of-Descriptions: Improving Code LLMs for VHDL Code Generation and Summarization.

Prashanth Vijayaraghavan, Apoorva Nitsure, Charles Mackin, Luyao Shi, Stefano Ambrogio, Arvind Haran, Viresh Paruthi, Ali El-Zein, Dan Coops, David Beymer, Tyler Baldwin, Ehsan Degan

Proceedings of the 2024 ACM/IEEE International Symposium on Machine Learning for CAD, 2024

2015

Solutions to IBM POWER8 verification challenges.

Klaus-Dieter Schubert, John M. Ludden, Salma Ayub, J. Behrend, Bishop Brock, Fady Copty, S. M. German, Oz Hershkovitz, H. Horbach, Jonathan R. Jackson, K. Keuerleber, J. Koesters, L. S. Leitner, G. B. Meil, Charles Meissner, Ronny Morad, Amir Nahir, Viresh Paruthi, Richard D. Peterson, Randall R. Pratt, Michal Rimon, John Schumann

IBM J. Res. Dev., 2015

Designer-level verification: an industrial experience story.

Stephen Bergman, Gabor Bobok, Walter Kowalski, Shlomit Koyfman, Shiri Moran, Ziv Nevo, Avigail Orni, Viresh Paruthi, Wolfgang Roesner, Gil Shurek, Vasantha Vuyyuru

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Verification of Galois field based circuits by formal reasoning based on computational algebraic geometry.

Alexey Lvov, Luis Alfonso Lastras-Montaño, Barry M. Trager, Viresh Paruthi, Robert Shadowen, Ali El-Zein

Formal Methods Syst. Des., 2014

Automatic Verification of Floating Point Units.

Udo Krautz, Viresh Paruthi, Anand Arunagiri, Sujeet Kumar, Shweta Pujar, Tina Babinsky

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2012

Formal verification of error correcting circuits using computational algebraic geometry.

Alexey Lvov, Luis Alfonso Lastras-Montaño, Viresh Paruthi, Robert Shadowen, Ali El-Zein

Proceedings of the Formal Methods in Computer-Aided Design, 2012

2011

Hybrid verification of a hardware modular reduction engine.

Jun Sawada, Peter Sandon, Viresh Paruthi, Jason Baumgartner, Michael L. Case, Hari Mony

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Large-scale application of formal verification: From fiction to fact.

Viresh Paruthi

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

Formal verification of arbiters using property strengthening and underapproximations.

Gadiel Auerbach, Fady Copty, Viresh Paruthi

Proceedings of 10th International Conference on Formal Methods in Computer-Aided Design, 2010

2009

Formal verification of correctness and performance of random priority-based arbiters.

Krishnan Kailas, Viresh Paruthi, Brian Monwai

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

2006

Scalable Sequential Equivalence Checking across Arbitrary Design Transformations .

Jason Baumgartner, Hari Mony, Viresh Paruthi, Robert Kanzelman, Geert Janssen

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

2005

Automatic Formal Verification of Fused-Multiply-Add FPUs.

Christian Jacobi, Kai Weber, Viresh Paruthi, Jason Baumgartner

Proceedings of the 2005 Design, 2005

Exploiting suspected redundancy without proving it.

Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman

Proceedings of the 42nd Design Automation Conference, 2005

Efficient Symbolic Simulation via Dynamic Scheduling, Don't Caring, and Case Splitting.

Viresh Paruthi, Christian Jacobi, Kai Weber

Proceedings of the Correct Hardware Design and Verification Methods, 2005

2004

Scalable Automated Verification via Expert-System Guided Transformations.

Hari Mony, Jason Baumgartner, Viresh Paruthi, Robert Kanzelman, Andreas Kuehlmann

Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

2002

Robust Boolean reasoning for equivalence checking and functional property verification.

Andreas Kuehlmann, Viresh Paruthi, Florian Krohm, Malay K. Ganai

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Functional verification of the POWER4 microprocessor and POWER4 multiprocessor system.

John M. Ludden, Wolfgang Roesner, Gerry M. Heiling, John R. Reysa, Jonathan R. Jackson, Bing-Lun Chu, Michael L. Behm, Jason Baumgartner, Richard D. Peterson, Jamee Abdulhafiz, William E. Bucy, John H. Klaus, Danny J. Klema, Tien N. Le, F. Danette Lewis, Philip E. Milling, Lawrence A. McConville, Bradley S. Nelson, Viresh Paruthi, Travis W. Pouarz, Audre D. Romonosky, Jeff Stuecheli, Kent D. Thompson, Dave W. Victor, Bruce Wile

IBM J. Res. Dev., 2002

2001

Circuit-based Boolean Reasoning.

Andreas Kuehlmann, Malay K. Ganai, Viresh Paruthi

Proceedings of the 38th Design Automation Conference, 2001

2000

Equivalence Checking Combining a Structural SAT-Solver, BDDs, and Simulation.

Viresh Paruthi, Andreas Kuehlmann

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

1998

Automatic data path abstraction for verification of large scale designs.

Viresh Paruthi, Nazanin Mansouri, Ranga Vemuri

Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998