Georgios Zervakis

Orcid: 0000-0001-8110-7122

Affiliations:
  • Karlsruhe Institute of Technology, Karlsruhe, Germany


According to our database1, Georgios Zervakis authored at least 54 papers between 2013 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Online presence:

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Bibliography

2024
TransAxx: Efficient Transformers with Approximate Computing.
CoRR, 2024

Embedding Hardware Approximations in Discrete Genetic-based Training for Printed MLPs.
CoRR, 2024

2023
Model-to-Circuit Cross-Approximation For Printed Machine Learning Classifiers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Co-Design of Approximate Multilayer Perceptron for Ultra-Resource Constrained Printed Circuits.
IEEE Trans. Computers, September, 2023

AdaPT: Fast Emulation of Approximate DNN Accelerators in PyTorch.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2023

Targeting DNN Inference Via Efficient Utilization of Heterogeneous Precision DNN Accelerators.
IEEE Trans. Emerg. Top. Comput., 2023

Hardware Approximate Techniques for Deep Neural Network Accelerators: A Survey.
ACM Comput. Surv., 2023

Hardware-Aware DNN Compression via Diverse Pruning and Mixed-Precision Quantization.
CoRR, 2023

On-sensor Printed Machine Learning Classification via Bespoke ADC and Decision Tree Co-Design.
CoRR, 2023

Bespoke Approximation of Multiplication-Accumulation and Activation Targeting Printed Multilayer Perceptrons.
Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Hardware-Aware Automated Neural Minimization for Printed Multilayer Perceptrons.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
Energy Efficient Edge Computing Enabled by Satisfaction Games and Approximate Computing.
IEEE Trans. Green Commun. Netw., 2022

Variability-Aware Approximate Circuit Synthesis via Genetic Optimization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Energy-Efficient DNN Inference on Approximate Accelerators Through Formal Property Exploration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Thermal-Aware Design for Approximate DNN Accelerators.
IEEE Trans. Computers, 2022

Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU.
IEEE Trans. Computers, 2022

Approximate Decision Trees For Machine Learning Classification on Tiny Printed Circuits.
Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Approximate Computing and the Efficient Machine Learning Expedition.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

Cross-Layer Approximation For Printed Machine Learning Circuits.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Enabling Efficient Inference of Convolutional Neural Networks via Approximation.
Proceedings of the Approximate Computing, 2022

2021
PROTON: Post-Synthesis Ferroelectric Thickness Optimization for NCFET Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Automated Design Approximation to Overcome Circuit Aging.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Impact of NCFET on Neural Network Accelerators.
IEEE Access, 2021

Positive/Negative Approximate Multipliers for DNN Accelerators.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

FeFET and NCFET for Future Neural Networks: Visions and Opportunities.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Reliability-Aware Quantization for Anti-Aging NPUs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Control Variate Approximation for DNN Accelerators.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Approximate Computing for ML: State-of-the-art, Challenges and Visions.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Weight-Oriented Approximation for Energy-Efficient Neural Network Inference Accelerators.
IEEE Trans. Circuits Syst., 2020

NPU Thermal Management.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Design Automation of Approximate Circuits With Runtime Reconfigurable Accuracy.
IEEE Access, 2020

2019
VADER: Voltage-Driven Netlist Pruning for Cross-Layer Approximate Arithmetic Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2019

Multi-Level Approximate Accelerator Synthesis Under Voltage Island Constraints.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

Optimizing SVM Classifier Through Approximate and High Level Synthesis Techniques.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

Co-design Implications of Cost-effective On-demand Acceleration for Cloud Healthcare Analytics: The AEGLE approach.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

A Design Flow Framework for Fully-Connected Neural Networks Rapid Prototyping.
Proceedings of the International Conference on Omni-Layer Intelligent Systems, 2019

2018
VOSsim: A Framework for Enabling Fast Voltage Overscaling Simulation for Approximate Computing Circuits.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Approximate Hybrid High Radix Encoding for Energy-Efficient Inexact Multipliers.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Walking through the Energy-Error Pareto Frontier of Approximate Multipliers.
IEEE Micro, 2018

2017
AEGLE's Cloud Infrastructure for Resource Monitoring and Containerized Accelerated Analytics.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

2016
Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst., 2016

Pre-Encoded Multipliers Based on Non-Redundant Radix-4 Signed-Digit Encoding.
IEEE Trans. Computers, 2016

Performance-power exploration of software-defined big data analytics: The AEGLE cloud backend.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016

2015
Delta DICE: A Double Node Upset resilient latch.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

Hybrid approximate multiplier architectures for improved power-accuracy trade-offs.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Approximate Multiplier Architectures Through Partial Product Perforation: Power-Area Tradeoffs Analysis.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014
FF-DICE: An 8T soft-error tolerant cell using Independent Dual Gate SOI FinFETs.
Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A high radix montgomery multiplier with concurrent error detection.
Proceedings of the 9th International Design and Test Symposium, 2014

An independent dual gate SOI FinFET soft-error resilient memory cell.
Proceedings of the 9th International Design and Test Symposium, 2014

High performance MAC designs.
Proceedings of the 9th International Design and Test Symposium, 2014

A segmentation-based BISR scheme.
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013
A radiation tolerant and self-repair memory cell.
Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013


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