Nidhi Agrawal

According to our database, Nidhi Agrawal authored at least 11 papers between 1995 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2026

Integrated finite element-based digital twin model and scalable computational feature transfer framework for structural dynamics and damage detection.

Nidhi Agrawal, Rehan Nath, Aashritha Lakshmi Mallampati, Keshav Goel, Shashank Gupta, Shuvendu Narayan Patel, Devendra Gokul Patil

J. Supercomput., June, 2026

2022

Improvements in Automated IC Socket Pin Defect Detection.

Vijayakumar Thangamariappan, Nidhi Agrawal, Jason Kim, Constantinos Xanthopoulos, Ken Butler, Ira Leventhal, Joe Xiao

Proceedings of the IEEE International Test Conference, 2022

2020

Automated Socket Anomaly Detection through Deep Learning.

Nidhi Agrawal, Min-Jian Yang, Constantinos Xanthopoulos, Vijayakumar Thangamariappan, Joe Xiao, Chee-Wah Ho, Keith Schaub, Ira Leventhal

Proceedings of the IEEE International Test Conference, 2020

2016

Understanding clinical and non-clinical decisions under uncertainty: a scenario-based survey.

Vlad V. Simianu, Margaret A. Grounds, Susan L. Joslyn, Jared E. LeClerc, Anne P. Ehlers, Nidhi Agrawal, Rafael Alfonso-Cristancho, Abraham D. Flaxman, David R. Flum

BMC Medical Informatics Decis. Mak., 2016

2013

Error in mathematical modelling and enhancement of sensing performance of electrostrictive capacitive sensors.

Om Prakash Thakur, Nidhi Agrawal

Proceedings of the Seventh International Conference on Sensing Technology, 2013

1999

A functional-level testability measure for register-level circuits and its estimation.

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal

Microprocess. Microsystems, 1999

1998

Adaptive Routing Based on Deadlock Recovery.

Nidhi Agrawal, C. P. Ravikumar

Proceedings of the Euro-Par '98 Parallel Processing, 1998

1997

An Euler Path Based Technique for Deadlock-free Multicasting.

Nidhi Agrawal, C. P. Ravikumar

Proceedings of the 1997 International Conference on Parallel Processing (ICPP '97), 1997

1996

Fault-tolerant routing in multiply twisted cube topology.

Nidhi Agrawal, C. P. Ravikumar

J. Syst. Archit., 1996

Efficient Delay Test Generation for Modular Circuits.

Nidhi Agrawal, Parul Agarwal, C. P. Ravikumar

Proceedings of the 6th Great Lakes Symposium on VLSI (GLS-VLSI '96), 1996

1995

A STAFAN-like functional testability measure for register-level circuits.

C. P. Ravikumar, Gurjeet S. Saund, Nidhi Agrawal

Proceedings of the 4th Asian Test Symposium (ATS '95), 1995