Constantinos Xanthopoulos

Orcid: 0000-0002-7815-9877

According to our database1, Constantinos Xanthopoulos authored at least 16 papers between 2014 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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Links

On csauthors.net:

Bibliography

2023
Machine Learning-Based Adaptive Outlier Detection for Underkill Reduction in Analog/RF IC Testing.
Proceedings of the 41st IEEE VLSI Test Symposium, 2023

2022
Improvements in Automated IC Socket Pin Defect Detection.
Proceedings of the IEEE International Test Conference, 2022

Zero Trust Approach to IC Manufacturing and Testing.
Proceedings of the IEEE International Test Conference, 2022

2021
On Improving Hotspot Detection Through Synthetic Pattern-Based Database Enhancement.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Trim Time Reduction in Analog/RF ICs Based on Inter-Trim Correlation.
Proceedings of the 39th IEEE VLSI Test Symposium, 2021

2020
Automated Socket Anomaly Detection through Deep Learning.
Proceedings of the IEEE International Test Conference, 2020

2019
Machine Learning-based Noise Classification and Decomposition in RF Transceivers.
Proceedings of the 37th IEEE VLSI Test Symposium, 2019

Subtle Anomaly Detection of Microscopic Probes using Deep learning based Image Completion.
Proceedings of the IEEE International Test Conference, 2019

Automated Die Inking through On-line Machine Learning.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Wafer-Level Adaptive Vmin Calibration Seed Forecasting.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018
Enhanced hotspot detection through synthetic pattern generation and design of experiments.
Proceedings of the 36th IEEE VLSI Test Symposium, 2018

2017
Automated die inking: A pattern recognition-based approach.
Proceedings of the IEEE International Test Conference, 2017

Wafer-level adaptive trim seed forecasting based on E-tests.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
Harnessing process variations for optimizing wafer-level probe-test flow.
Proceedings of the 2016 IEEE International Test Conference, 2016

2015
Low-Cost Analog/RF IC Testing Through Combined Intra- and Inter-Die Correlation Models.
IEEE Des. Test, 2015

2014
IC laser trimming speed-up through wafer-level spatial correlation modeling.
Proceedings of the 2014 International Test Conference, 2014


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