Nor Zaidi Haron

Affiliations:
  • Universiti Teknikal Malaysia Melaka, Malaysia
  • Delft University of Technology, The Netherlands


According to our database1, Nor Zaidi Haron authored at least 11 papers between 2009 and 2015.

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Bibliography

2015
Testing Open Defects in Memristor-Based Memories.
IEEE Trans. Computers, 2015

2012
DfT schemes for resistive open defects in RRAMs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories.
ACM J. Emerg. Technol. Comput. Syst., 2011

NBTI Monitoring and Design for Reliability in Nanoscale Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories.
Proceedings of the Design, Automation and Test in Europe, 2011

On Defect Oriented Testing for Hybrid CMOS/Memristor Memory.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
ECC design for fault-tolerant crossbar memories: A case study.
Proceedings of the 5th International Design and Test Workshop, 2010

High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

2009
Emerging non-CMOS nanoelectronic devices - What are they?.
Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009

Residue-based code for reliable hybrid memories.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009


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