Said Hamdioui

According to our database1, Said Hamdioui authored at least 197 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

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Bibliography

2020
Public-Key Based Authentication Architecture for IoT Devices Using PUF.
CoRR, 2020

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.
CoRR, 2020

2019
Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM.
IEEE Trans. VLSI Syst., 2019

Challenges and Solutions in Emerging Memory Testing.
IEEE Trans. Emerging Topics Comput., 2019

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.
J. Low Power Electronics, 2019

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs.
Journal of Circuits, Systems, and Computers, 2019

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.
CoRR, 2019

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era.
IEEE Access, 2019

CIM-SIM: Computation In Memory SIMuIator.
Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

A computation-in-memory accelerator based on resistive devices.
Proceedings of the International Symposium on Memory Systems, 2019

Software-Based Mitigation for Memory Address Decoder Aging.
Proceedings of the IEEE Latin American Test Symposium, 2019

Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Memristive Device Based Circuits for Computation-in-Memory Architectures.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Efficient Methodology for ISO26262 Functional Safety Verification.
Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Untestable faults identification in GPGPUs for safety-critical applications.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.
Proceedings of the 24th IEEE European Test Symposium, 2019

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs.
Proceedings of the 24th IEEE European Test Symposium, 2019

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder.
Proceedings of the 24th IEEE European Test Symposium, 2019

Rebooting Computing: The Challenges for Test and Reliability.
Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Time-division Multiplexing Automata Processor.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Methodology for Application-Dependent Degradation Analysis of Memory Timing.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification.
Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018
Guest Editorial Memristive-Device-Based Computing.
IEEE Trans. VLSI Syst., 2018

A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2018

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.
Microelectron. Reliab., 2018

Impact and mitigation of SRAM read path aging.
Microelectron. Reliab., 2018

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories.
I. J. Circuit Theory and Applications, 2018

Ionizing radiation modeling in DRAM transistors.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Electrical Modeling of STT-MRAM Defects.
Proceedings of the IEEE International Test Conference, 2018

Testing Resistive Memories: Where are We and What is Missing?
Proceedings of the IEEE International Test Conference, 2018

Device aging: A reliability and security concern.
Proceedings of the 23rd IEEE European Test Symposium, 2018

Memristive devices for computation-in-memory.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Degradation analysis of high performance 14nm FinFET SRAM.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
On the Implementation of Computation-in-Memory Parallel Adder.
IEEE Trans. VLSI Syst., 2017

Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.
IEEE Trans. VLSI Syst., 2017

Editorial.
IEEE Trans. VLSI Syst., 2017

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
IEEE Trans. VLSI Syst., 2017

Resistive Random Access Memory Variability and Its Mitigation Schemes.
J. Low Power Electronics, 2017

Memristive devices for computing: Beyond CMOS and beyond von Neumann.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Tight Bounds in Message Delays Despite Faults in a Class of Line Digraph Networks.
Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Standards-based tools and services for building lifelong learning pathways.
Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

Interconnect networks for resistive computing architectures.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Memristive devices: Technology, design automation and computing frontiers.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Region based containers - A new paradigm for the analysis of fault tolerant networks.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

On the robustness of memristor based logic gates.
Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Mitigation of sense amplifier degradation using input switching.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Memristor for computing: Myth or reality?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Test and Reliability of Emerging Non-volatile Memories.
Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016
Alternative Architectures Toward Reliable Memristive Crossbar Memories.
IEEE Trans. VLSI Syst., 2016

SIERRA - Simulation environment for memory redundancy algorithms.
Simulation Modelling Practice and Theory, 2016

Editorial Note on Memristor Models, Circuits and Architectures.
IJUC, 2016

RRAM variability and its mitigation schemes.
Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Skeleton-based design and simulation flow for Computation-in-Memory architectures.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Synthesizing HDL to memristor technology: A generic framework.
Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Instruction cache aging mitigation through Instruction Set Encoding.
Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Non-volatile look-up table based FPGA implementations.
Proceedings of the 11th International Design & Test Symposium, 2016

ETS 2016 foreword.
Proceedings of the 21th IEEE European Test Symposium, 2016

Read path degradation analysis in SRAM.
Proceedings of the 21th IEEE European Test Symposium, 2016

Boolean logic gate exploration for memristor crossbar.
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Comparative BTI analysis for various sense amplifier designs.
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015
Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching.
ACM Trans. Design Autom. Electr. Syst., 2015

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Testing Open Defects in Memristor-Based Memories.
IEEE Trans. Computers, 2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.
IEEE Design & Test, 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.
IEEE Design & Test, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Computation in Memory for Data-Intensive Applications: Beyond CMOS and beyond Von- Neumann.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Interconnect networks for memristor crossbar.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Computation-in-memory based parallel adder.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Design dependent SRAM PUF robustness analysis.
Proceedings of the 16th Latin-American Test Symposium, 2015

SW-based transparent in-field memory testing.
Proceedings of the 16th Latin-American Test Symposium, 2015

Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann".
Proceedings of the 10th International Design & Test Symposium, 2015

BTI analysis of SRAM write driver.
Proceedings of the 10th International Design & Test Symposium, 2015

Fast boolean logic mapped on memristor crossbar.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

On resistive open defect detection in DRAMs: The charge accumulation effect.
Proceedings of the 20th IEEE European Test Symposium, 2015

Electronics and computing in nano-era: The good, the bad and the challenging.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.
Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Memristor based computation-in-memory architecture for data-intensive applications.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Layout-Based Refined NPSF Model for DRAM Characterization and Testing.
IEEE Trans. VLSI Syst., 2014

Testing Methods for PUF-Based Secure Key Storage Circuits.
J. Electronic Testing, 2014

Quality versus cost analysis for 3D Stacked ICs.
Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.
Proceedings of the 2014 International Test Conference, 2014

Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures.
Proceedings of the IEEE 15th International Conference on High Performance Switching and Routing, 2014

Memristor based memories: Technology, design and test.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

3D/ 2.5D stacked IC cost modeling and test flow selection.
Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Shortest path reduction in a class of uniform fault tolerant networks.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Security methods in fault tolerant modified line graph based networks.
Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Interconnect test for 3D stacked memory-on-logic.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Bias Temperature Instability analysis of FinFET based SRAM cells.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hacking and protecting IC hardware.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Testing PUF-based secure key storage circuits.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks.
Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2013
Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN).
J. Electronic Testing, 2013

Exploring test opportunities for memory and interconnects in 3D ICs.
Proceedings of the 8th International Design and Test Symposium, 2013

Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms.
Proceedings of the 8th International Design and Test Symposium, 2013

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013

BTI impact on SRAM sense amplifier.
Proceedings of the 8th International Design and Test Symposium, 2013

Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs.
Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.
Proceedings of the 18th IEEE European Test Symposium, 2013

Bias temperature instability analysis in SRAM decoder.
Proceedings of the 18th IEEE European Test Symposium, 2013

Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?
Proceedings of the 18th IEEE European Test Symposium, 2013

Impact of mid-bond testing in 3D stacked ICs.
Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Is TSV-based 3D integration suitable for inter-die memory repair?
Proceedings of the Design, Automation and Test in Europe, 2013

Reliability challenges of real-time systems in forthcoming technology nodes.
Proceedings of the Design, Automation and Test in Europe, 2013

An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase.
Proceedings of the 22nd Asian Test Symposium, 2013

Using 3D-COSTAR for 2.5D test cost optimization.
Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012
Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.
J. Electronic Testing, 2012

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.
J. Electronic Testing, 2012

Testing Embedded Memories: A Survey.
Proceedings of the Mathematical and Engineering Methods in Computer Science, 2012

VLSI Test technology: Why is the field not sexy enough?
Proceedings of the 17th IEEE European Test Symposium, 2012

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Modeling SRAM start-up behavior for Physical Unclonable Functions.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

BTI impact on logical gates in nano-scale CMOS technology.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

TSV based 3D stacked ICs: Opportunities and challenges.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

DfT schemes for resistive open defects in RRAMs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories.
JETC, 2011

Generic, orthogonal and low-cost March Element based memory BIST.
Proceedings of the 2011 IEEE International Test Conference, 2011

Modeling and mitigating NBTI in nanoscale circuits.
Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

On modeling and optimizing cost in 3D Stacked-ICs.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

ReverseAge: An online NBTI combating technique using time borrowing.
Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.
Proceedings of the 16th European Test Symposium, 2011

Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.
Proceedings of the 16th European Test Symposium, 2011

A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

NBTI Monitoring and Design for Reliability in Nanoscale Circuits.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Reducing Test Power for Embedded Memories.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Stacking order impact on overall 3D die-to-wafer Stacked-IC cost.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Influence of parasitic memory effect on single-cell faults in SRAMs.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories.
Proceedings of the Design, Automation and Test in Europe, 2011

Testing for Parasitic Memory Effect in SRAMs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

On Defect Oriented Testing for Hybrid CMOS/Memristor Memory.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

Yield Improvement and Test Cost Optimization for 3D Stacked ICs.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

A New Test Paradigm for Semiconductor Memories in the Nano-Era.
Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010
Bit line coupling memory tests for single-cell fails in SRAMs.
Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.
Proceedings of the 2011 IEEE International Test Conference, 2010

Detecting memory faults in the presence of bit line coupling in SRAM devices.
Proceedings of the 2011 IEEE International Test Conference, 2010

Temperature dependence of NBTI induced delay.
Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

ECC design for fault-tolerant crossbar memories: A case study.
Proceedings of the 5th International Design and Test Workshop, 2010

MBIST architecture framework based on orthogonal constructs.
Proceedings of the 5th International Design and Test Workshop, 2010

High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Advanced embedded memory testing: Reducing the defect per million level at lower test cost.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Low-cost, customized and flexible SRAM MBIST engine.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Using a CISC microcontroller to test embedded memories.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

NBTI modeling in the framework of temperature variation.
Proceedings of the Design, Automation and Test in Europe, 2010

Memory testing with a RISC microcontroller.
Proceedings of the Design, Automation and Test in Europe, 2010

Test Cost Analysis for 3D Die-to-Wafer Stacking.
Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009
Instruction-Level Fault Tolerance Configurability.
Signal Processing Systems, 2009

Emerging non-CMOS nanoelectronic devices - What are they?.
Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009

Residue-based code for reliable hybrid memories.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.
Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault Diagnosis Using Test Primitives in Random Access Memories.
Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008
Test Set Development for Cache Memory in Modern Microprocessors.
IEEE Trans. VLSI Syst., 2008

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.
Proceedings of the 2008 IEEE International Test Conference, 2008

2007
Optimizing Test Length for Soft Faults in DRAM Devices.
Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

PPM Reduction on Embedded Memories in System on Chip.
Proceedings of the 12th European Test Symposium, 2007

Manifestation of Precharge Faults in High Speed DRAM Devices.
Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Opens and Delay Faults in CMOS RAM Address Decoders.
IEEE Trans. Computers, 2006

DRAM-Specific Space of Memory Tests.
Proceedings of the 2006 IEEE International Test Conference, 2006

Space of DRAM fault models and corresponding testing.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005
New data-background sequences and their industrial evaluation for word-oriented random-access memories.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Impact of stresses on the fault coverage of memory tests.
Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Framework for Fault Analysis and Test Generation in DRAMs.
Proceedings of the 2005 Design, 2005

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Memory Fault Modeling Trends: A Case Study.
J. Electronic Testing, 2004

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.
Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

The State-of-Art and Future Trends in Testing Embedded Memories.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

The Effectiveness of the Scan Test and Its New Variants.
Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.
Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Tests for address decoder delay faults in RAMs due to inter-gate opens.
Proceedings of the 9th European Test Symposium, 2004

Evaluation of Intra-Word Faults in Word-Oriented RAMs.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003
Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.
J. Electronic Testing, 2003

Detecting Intra-Word Faults in Word-Oriented Memories.
Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Fault Primitive Based Analysis of Linked Faults in RAMs.
Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

March SL: A Test For All Static Linked Memory Faults.
Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002
Thorough testing of any multiport memory with linear tests.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Efficient Tests for Realistic Faults in Dual-Port SRAMs.
IEEE Trans. Computers, 2002

Testing Static and Dynamic Faults in Random Access Memories.
Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

March SS: A Test for All Static Simple RAM Faults.
Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001
Realistic Fault Models and Test Procedures for Multi-Port SRAMs.
Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Detecting Unique Faults in Multi-port SRAMs.
Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000
Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.
J. Electronic Testing, 2000

March Tests for Realistic Faults in Two-Port Memories.
Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

An experimental analysis of spot defects in SRAMs: realistic fault models and tests.
Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999
Port interference faults in two-port memories.
Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

March Tests for Word-Oriented Two-Port Memories.
Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998
Fault Models and Tests for Two-Port Memories.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Consequences of port restrictions on testing two-port memories.
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998


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