Said Hamdioui

IEEE Trans. Circuits Syst. II Express Briefs, April, 2024

Survey on Architectural Attacks: A Unified Classification and Attack Model.

[BibT_eX]

[DOI]

ACM Comput. Surv., February, 2024

High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics.

[BibT_eX]

[DOI]

CoRR, 2024

Spin Wave Threshold Gate.

[BibT_eX]

[DOI]

CoRR, 2024

Reliable and Energy-Efficient Diabetic Retinopathy Screening Using Memristor-Based Neural Networks.

[BibT_eX]

[DOI]

Sumit Diware

Koteswararao Chilakala

Rajiv V. Joshi

Rajendra Bishnoi

IEEE Access, 2024

2023

A Survey on Machine Learning in Hardware Security.

[BibT_eX]

[DOI]

Josie E. Rodriguez Condia

ACM J. Emerg. Technol. Comput. Syst., April, 2023

Using STLs for Effective In-Field Test of GPUs.

[BibT_eX]

[DOI]

Juan-David Guerrero-Balaguera

Ahmet Çagri Bagbaga

Matteo Sonza Reorda

IEEE Des. Test, April, 2023

Accurate and Energy-Efficient Bit-Slicing for RRAM-Based Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput. Intell., February, 2023

Severity-Based Hierarchical ECG Classification Using Neural Networks.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., February, 2023

A Lightweight Architecture for Real-Time Neuronal-Spike Classification.

[BibT_eX]

[DOI]

Muhammad Ali Siddiqi

David Vrijenhoek

Lennart P. L. Landsmeer

CoRR, 2023

An In-Memory Architecture for High-Performance Long-Read Pre-Alignment Filtering.

[BibT_eX]

[DOI]

CoRR, 2023

Efficient Signed Arithmetic Multiplication on Memristor-Based Crossbar.

[BibT_eX]

[DOI]

IEEE Access, 2023

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes.

[BibT_eX]

[DOI]

Shayesteh Masoumian

Roel Maes

Rui Wang

Karthik Keni Yerriswamy

Geert Jan Schrijen

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

On the Reliability of RRAM-Based Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

A Case for Genome Analysis Where Genomes Reside.

[BibT_eX]

[DOI]

Taha Shahroodi

Stephan Wong

Jan Andrés Galvan Hernández

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

RattlesnakeJake: A Fast and Accurate Pre-alignment Filter Suitable for Computation-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Devices and Architectures for Efficient Computing In-Memory (CIM) Design.

[BibT_eX]

[DOI]

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2023

Spin Wave Threshold Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM International Symposium on Nanoscale Architectures, 2023

Swordfish: A Framework for Evaluating Deep Neural Network-based Basecalling using Computation-In-Memory with Non-Ideal Memristors.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

Magnetic Coupling Based Test Development for Contact and Interconnect Defects in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

Device-Aware Test for Ion Depletion Defects in RRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2023

Energy-efficient Computation-In-Memory Architecture using Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Microelectronics, 2023

Data Background-Based Test Development for All Interconnect and Contact Defects in RRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Dependability of Future Edge-AI Processors: Pandora's Box.

[BibT_eX]

[DOI]

Jan Richter-Brockmann

Proceedings of the IEEE European Test Symposium, 2023

Online Fault Detection and Diagnosis in RRAM.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Memristor-Based Lightweight Encryption.

[BibT_eX]

[DOI]

Muhammad Ali Siddiqi

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

A Pre-Silicon Power Leakage Assessment Based on Generative Adversarial Networks.

[BibT_eX]

[DOI]

Proceedings of the 26th Euromicro Conference on Digital System Design, 2023

SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph Processing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Device-Aware Test for Back-Hopping Defects in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Lightspeed Binary Neural Networks using Optical Phase-Change Materials.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

PetaOps/W edge-AI $\mu$ Processors: Myth or reality?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Characterization and Test of Intermittent Over RESET in RRAMs.

[BibT_eX]

[DOI]

Letícia Maria Veiras Bolzani Poehls

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

Device Aware Diagnosis for Unique Defects in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE Asian Test Symposium, 2023

SieveMem: A Computation-in-Memory Architecture for Fast and Accurate Pre-Alignment.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE International Conference on Application-specific Systems, 2023

Read-disturb Detection Methodology for RRAM-based Computation-in-Memory Architecture.

[BibT_eX]

[DOI]

Mohammad Amin Yaldagard

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

A 115.1 TOPS/W, 12.1 TOPS/mm<sup>2</sup> Computation-in-Memory using Ring-Oscillator based ADC for Edge AI.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

Mapping-aware Biased Training for Accurate Memristor-based Neural Networks.

[BibT_eX]

[DOI]

Proceedings of the 5th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2023

2022

Instruction flow-based detectors against fault injection attacks.

[BibT_eX]

[DOI]

Marcelo Brandalero

Microprocess. Microsystems, October, 2022

Spin Wave Based Approximate Computing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Non-Binary Spin Wave Based Circuit Design.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

APmap: An Open-Source Compiler for Automata Processors.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Characterization, Modeling, and Test of Intermediate State Defects in STT-MRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Energy-efficient In-Memory Address Calculation.

[BibT_eX]

[DOI]

ACM Trans. Archit. Code Optim., 2022

Reliability aspects of binary vector-matrix-multiplications using ReRAM devices.

[BibT_eX]

[DOI]

Neuromorph. Comput. Eng., 2022

MNEMOSENE: Tile Architecture and Simulator for Memristor-based Computation-in-memory.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

A Voltage-Controlled, Oscillation-Based ADC Design for Computation-in-Memory Architectures Using Emerging ReRAMs.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Guest Editorial: Computation-In-Memory (CIM): from Device to Applications.

[BibT_eX]

[DOI]

Elena I. Vatajelu

Alberto Bosio

ACM J. Emerg. Technol. Comput. Syst., 2022

A Survey on Memory-centric Computer Architectures.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2022

Defects, Fault Modeling, and Test Development Framework for RRAMs.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Poehls

ACM J. Emerg. Technol. Comput. Syst., 2022

CONVOLVE: Smart and seamless design of smart edge processors.

[BibT_eX]

[DOI]

CoRR, 2022

BCIM: Efficient Implementation of Binary Neural Network Based on Computation in Memory.

[BibT_eX]

[DOI]

CoRR, 2022

Assessing the Security of the IEEE 802.15.6 Standard for Medical BANs.

[BibT_eX]

[DOI]

CoRR, 2022

Improving the Security of the IEEE 802.15.6 Standard for Medical BANs.

[BibT_eX]

[DOI]

IEEE Access, 2022

Demeter: A Fast and Energy-Efficient Food Profiler Using Hyperdimensional Computing in Memory.

[BibT_eX]

[DOI]

IEEE Access, 2022

Rapid Design-Space Exploration for Low-Power Manycores Under Process Variation Utilizing Machine Learning.

[BibT_eX]

[DOI]

IEEE Access, 2022

Special Session: STT-MRAMs: Technology, Design and Test.

[BibT_eX]

[DOI]

Proceedings of the 40th IEEE VLSI Test Symposium, 2022

System Design for Computation-in-Memory: From Primitive to Complex Functions.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Dealing with Non-Idealities in Memristor Based Computation-In-Memory Designs.

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

Energy-Efficient SNN Implementation Using RRAM-Based Computation In-Memory (CIM).

[BibT_eX]

[DOI]

Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

On BTI Aging Rejuvenation in Memory Address Decoders.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Exploring an On-Chip Sensor to Detect Unique Faults in RRAMs.

[BibT_eX]

[DOI]

Thiago Santos Copetti

Proceedings of the 23rd IEEE Latin American Test Symposium, 2022

Accelerating RRAM Testing with a Low-cost Computation-in-Memory based DFT.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Structured Test Development Approach for Computation-in-Memory Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2022

Recent Trends and Perspectives on Defect-Oriented Testing.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

KrakenOnMem: a memristor-augmented HW/SW framework for taxonomic profiling.

[BibT_eX]

[DOI]

Proceedings of the ICS '22: 2022 International Conference on Supercomputing, Virtual Event, June 28, 2022

Would Magnonic Circuits Outperform CMOS Counterparts?

[BibT_eX]

[DOI]

Nicoleta Cucu Laurenciu

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

Hierarchical Memory Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

Smart Redundancy Schemes for ANNs Against Fault Attacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

RRAM Crossbar-Based Fault-Tolerant Binary Neural Networks (BNNs).

[BibT_eX]

[DOI]

Artemis Zografou

Proceedings of the IEEE European Test Symposium, 2022

PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory.

[BibT_eX]

[DOI]

Christopher Münch

Mehdi B. Tahoori

Proceedings of the IEEE European Test Symposium, 2022

Exploiting PUF Variation to Detect Fault Injection Attacks.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Referencing-in-Array Scheme for RRAM-based CIM Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Reliability Analysis of FinFET-Based SRAM PUFs for 16nm, 14nm, and 7nm Technology Nodes.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Using Hopfield Networks to Correct Instruction Faults.

[BibT_eX]

[DOI]

Proceedings of the IEEE 31st Asian Test Symposium, 2022

CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021

Hard-to-Detect Fault Analysis in FinFET SRAMs.

[BibT_eX]

[DOI]

Letícia Maria Bolzani Poehls

IEEE Trans. Very Large Scale Integr. Syst., 2021

Applying Thermal Side-Channel Attacks on Asymmetric Cryptography.

[BibT_eX]

[DOI]

Abdullah Aljuffri

Marc Zwalua

IEEE Trans. Very Large Scale Integr. Syst., 2021

Defect and Fault Modeling Framework for STT-MRAM Testing.

[BibT_eX]

[DOI]

Siddharth Rao

IEEE Trans. Emerg. Top. Comput., 2021

SRIF: Scalable and Reliable Integrate and Fire Circuit ADC for Memristor-Based CIM Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Spin Wave Normalization Toward All Magnonic Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

Evaluation of Single Event Upset Susceptibility of FinFET-based SRAMs with Weak Resistive Defects.

[BibT_eX]

[DOI]

Thiago Copetti

Letícia Maria Bolzani Poehls

Tiago Roberto Balen

J. Electron. Test., 2021

Review of Manufacturing Process Defects and Their Effects on Memristive Devices.

[BibT_eX]

[DOI]

Susanne Hoffmann-Eifert

J. Electron. Test., 2021

Multi-Bit Blinding: A Countermeasure for RSA Against Side Channel Attacks.

[BibT_eX]

[DOI]

Proceedings of the 39th IEEE VLSI Test Symposium, 2021

Towards Reliable In-Memory Computing: From Emerging Devices to Post-von-Neumann Architectures.

[BibT_eX]

[DOI]

Proceedings of the 29th IFIP/IEEE International Conference on Very Large Scale Integration, 2021

Deterministic and Statistical Strategies to Protect ANNs against Fault Injection Attacks.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Privacy, Security and Trust, 2021

Evaluating the Impact of Process Variation on RRAMs.

[BibT_eX]

[DOI]

E. Brum

Thiago Santos Copetti

H. Jiayi

Fabian Vargas

Proceedings of the 22nd IEEE Latin American Test Symposium, 2021

Testing STT-MRAM: Manufacturing Defects, Fault Models, and Test Solutions.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

An automated formal-based approach for reducing undetected faults in ISO 26262 hardware compliant designs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Tile Architecture and Hardware Implementation for Computation-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

LightRoAD: Lightweight Rowhammer Attack Detector.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021

Achieving Wave Pipelining in Spin Wave Technology.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Low-Power Memristor-Based Computing for Edge-AI Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Spin Wave Based Full Adder.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

Flip Flop Weighting: A technique for estimation of safety metrics in Automotive Designs.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Spin Wave Based 4-2 Compressor.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Conference on Electronics, 2021

Detecting Random Read Faults to Reduce Test Escapes in FinFET SRAMs.

[BibT_eX]

[DOI]

Leticia Bolzani Poehls

Proceedings of the 26th IEEE European Test Symposium, 2021

Intermittent Undefined State Fault in RRAMs.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE European Test Symposium, 2021

Emerging Computing Devices: Challenges and Opportunities for Test and Reliability<sup>*</sup>.

[BibT_eX]

[DOI]

Muhammad Abdullah Hanif

Proceedings of the 26th IEEE European Test Symposium, 2021

Power Side Channel Attacks: Where Are We Standing?

[BibT_eX]

[DOI]

Abdullah Aljuffri

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Improving the Detection of Undefined State Faults in FinFET SRAMs.

[BibT_eX]

[DOI]

G. Cardoso Medeiros

Thiago Santos Copetti

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Impact of Data Pre-Processing Techniques on Deep Learning Based Power Attacks.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Protecting IoT Devices through a Hardware-driven Memory Verification.

[BibT_eX]

[DOI]

Hans Okkerman

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Revealing the Secrets of Spiking Neural Networks: The Case of Izhikevich Neuron.

[BibT_eX]

[DOI]

Proceedings of the 24th Euromicro Conference on Digital System Design, 2021

Modeling Soft-Error Reliability Under Variability.

[BibT_eX]

[DOI]

Aneesh Balakrishnan

Proceedings of the 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2021

Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

GRINCH: A Cache Attack against GIFT Lightweight Cipher.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Perspectives on Emerging Computation-in-Memory Paradigms.

[BibT_eX]

[DOI]

Shubham Rai

Mengyun Liu

Debjyoti Bhattacharjee

Krishnendu Chakrabarty

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Fan-out of 2 Triangle Shape Spin Wave Logic Gates.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Density Enhancement of RRAMs using a RESET Write Termination for MLC Operation.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Unbalanced Bit-slicing Scheme for Accurate Memristor-based Neural Network Architecture.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2021

2020

Skeleton-Based Synthesis Flow for Computation-in-Memory Architectures.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2020

A Classification of Memory-Centric Computing.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2020

Public-Key Based Authentication Architecture for IoT Devices Using PUF.

[BibT_eX]

[DOI]

CoRR, 2020

Survey on STT-MRAM Testing: Failure Mechanisms, Fault Models, and Tests.

[BibT_eX]

[DOI]

CoRR, 2020

In-Memory Database Query.

[BibT_eX]

[DOI]

Iason Giannopoulos

Abhairaj Singh

Manuel Le Gallo

Vara Prasad Jonnalagadda

Abu Sebastian

Adv. Intell. Syst., 2020

An Energy-Efficient Current-Controlled Write and Read Scheme for Resistive RAMs (RRAMs).

[BibT_eX]

[DOI]

IEEE Access, 2020

Special Session: AutoSoC - A Suite of Open-Source Automotive SoC Benchmarks.

[BibT_eX]

[DOI]

Sarath Mohanachandran Nair

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

Special Session - Emerging Memristor Based Memory and CIM Architecture: Test, Repair and Yield Analysis.

[BibT_eX]

[DOI]

Ying Wang

Huawei Li

Proceedings of the 38th IEEE VLSI Test Symposium, 2020

S-NET: A Confusion Based Countermeasure Against Power Attacks for SBOX.

[BibT_eX]

[DOI]

Abdullah Aljuffri

Pradeep Venkatachalam

Cezar Reinbrecht

Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

Evaluating the Impact of Ionizing Particles on FinFET -based SRAMs with Weak Resistive Defects.

[BibT_eX]

[DOI]

Thiago Copetti

Leticia Bolzani Poehls

Tiago R. Balen

Proceedings of the IEEE Latin-American Test Symposium, 2020

Characterization, Modeling and Test of Synthetic Anti-Ferromagnet Flip Defect in STT-MRAMs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2020

Efficient Organization of Digital Periphery to Support Integer Datatype for Memristor-Based CIM.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Guard-NoC: A Protection Against Side-Channel Attacks for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

2-Output Spin Wave Programmable Logic Gate.

[BibT_eX]

[DOI]

Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

RNN-Based Detection of Fault Attacks on RSA.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Yield Estimation of a Memristive Sensor Array.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

4-output Programmable Spin Wave Logic Gate.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

Device-Aware Test for Emerging Memories: Enabling Your Test Program for DPPB Level.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Determined-Safe Faults Identification: A step towards ISO26262 hardware compliant designs.

[BibT_eX]

[DOI]

Gennaro Severino Rodrigues

Proceedings of the IEEE European Test Symposium, 2020

LiD-CAT: A Lightweight Detector for Cache ATtacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Modeling Static Noise Margin for FinFET based SRAM PUFs.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

G-PUF: An Intrinsic PUF Based on GPU Error Signatures.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Testing Scouting Logic-Based Computation-in-Memory Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

eSRAM Reliability: Why is it still not optimally solved?

[BibT_eX]

[DOI]

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms.

[BibT_eX]

[DOI]

Alberto Bosio

Ian O'Connor

Fernanda Lima Lima

Proceedings of the 15th Design & Technology of Integrated Systems in Nanoscale Era, 2020

On the Analysis of Real-time Operating System Reliability in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

A Security Verification Template to Assess Cache Architecture Vulnerabilities.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2020

Impact of Magnetic Coupling and Density on STT-MRAM Performance.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

A DFT Scheme to Improve Coverage of Hard-to-Detect Faults in FinFET SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

n-bit Data Parallel Spin Wave Logic Gate.

[BibT_eX]

[DOI]

Heinrich Theodor Vierhaus

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

Mitigation of Sense Amplifier Degradation Using Skewed Design.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems.

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

The Power of Computation-in-Memory Based on Memristive Devices.

[BibT_eX]

[DOI]

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

Parametric and Functional Degradation Analysis of Complete 14-nm FinFET SRAM.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Challenges and Solutions in Emerging Memory Testing.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2019

System-Level Sub-20 nm Planar and FinFET CMOS Delay Modelling for Supply and Threshold Voltage Scaling Under Process Variation.

[BibT_eX]

[DOI]

Sohaib Majzoub

J. Low Power Electron., 2019

Configurable Operational Amplifier Architectures Based on Oxide Resistive RAMs.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2019

Energy Optimization for Large-Scale 3D Manycores in the Dark-Silicon Era.

[BibT_eX]

[DOI]

IEEE Access, 2019

CIM-SIM: Computation In Memory SIMuIator.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Workshop on Software and Compilers for Embedded Systems, 2019

Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2019

A computation-in-memory accelerator based on resistive devices.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

Software-Based Mitigation for Memory Address Decoder Aging.

[BibT_eX]

[DOI]

Proceedings of the IEEE Latin American Test Symposium, 2019

Testing Computation-in-Memory Architectures Based on Emerging Memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

Device-Aware Test: A New Test Approach Towards DPPB Level.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2019

IEEE European Test Symposium (ETS).

[BibT_eX]

[DOI]

Elena Ioana Vatajelu

Proceedings of the IEEE International Test Conference, 2019

Reliability Modeling and Mitigation for Embedded Memories.

[BibT_eX]

[DOI]

Innocent Okwudili Agbo

Proceedings of the IEEE International Test Conference, 2019

Memristive Device Modeling and Circuit Design Exploration for Computation-in-Memory.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Memristive Device Based Circuits for Computation-in-Memory Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Efficient Methodology for ISO26262 Functional Safety Verification.

[BibT_eX]

[DOI]

Josie E. Rodriguez Condia

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Untestable faults identification in GPGPUs for safety-critical applications.

[BibT_eX]

[DOI]

Matteo Sonza Reorda

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Pinhole Defect Characterization and Fault Modeling for STT-MRAM Testing.

[BibT_eX]

[DOI]

Siddharth Rao

Proceedings of the 24th IEEE European Test Symposium, 2019

DFT Scheme for Hard-to-Detect Faults in FinFET SRAMs.

[BibT_eX]

[DOI]

Leticia Bolzani Poehls

Gennaro Severino Rodrigues

Proceedings of the 24th IEEE European Test Symposium, 2019

Hardware-Based Aging Mitigation Scheme for Memory Address Decoder.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

Rebooting Computing: The Challenges for Test and Reliability.

[BibT_eX]

[DOI]

Alberto Bosio

Ian O'Connor

Fernanda Lima Kastensmidt

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Time-division Multiplexing Automata Processor.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Methodology for Application-Dependent Degradation Analysis of Memory Timing.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Applications of Computation-In-Memory Architectures based on Memristive Devices.

[BibT_eX]

[DOI]

Fernando García-Redondo

Geethan Karunaratne

Abbas Rahimi

Luca Benini

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Combining Fault Analysis Technologies for ISO26262 Functional Safety Verification.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE Asian Test Symposium, 2019

2018

Guest Editorial Memristive-Device-Based Computing.

[BibT_eX]

[DOI]

Pierre-Emmanuel Gaillardon

Dietmar Fey

Tajana Simunic Rosing

IEEE Trans. Very Large Scale Integr. Syst., 2018

A Mapping Methodology of Boolean Logic Circuits on Memristor Crossbar.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs.

[BibT_eX]

[DOI]

G. Cardoso Medeiros

Fabian Vargas

Microelectron. Reliab., 2018

Impact and mitigation of SRAM read path aging.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

State of the art and challenges for test and reliability of emerging nonvolatile resistive memories.

[BibT_eX]

[DOI]

Elena Ioana Vatajelu

Peyman Pouyan

Int. J. Circuit Theory Appl., 2018

Ionizing radiation modeling in DRAM transistors.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Latin-American Test Symposium, 2018

Electrical Modeling of STT-MRAM Defects.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Testing Resistive Memories: Where are We and What is Missing?

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2018

Device aging: A reliability and security concern.

[BibT_eX]

[DOI]

Hans-Joachim Wunderlich

Naghmeh Karimi

Proceedings of the 23rd IEEE European Test Symposium, 2018

Memristive devices for computation-in-memory.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Degradation analysis of high performance 14nm FinFET SRAM.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017

On the Implementation of Computation-in-Memory Parallel Adder.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Impact and Mitigation of Sense Amplifier Aging Degradation Using Realistic Workloads.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Editorial.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

Resistive Random Access Memory Variability and Its Mitigation Schemes.

[BibT_eX]

[DOI]

J. Low Power Electron., 2017

Memristive devices for computing: Beyond CMOS and beyond von Neumann.

[BibT_eX]

[DOI]

Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

Scouting Logic: A Novel Memristor-Based Logic Design for Resistive Computing.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Tight Bounds in Message Delays Despite Faults in a Class of Line Digraph Networks.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Pervasive Systems, 2017

Standards-based tools and services for building lifelong learning pathways.

[BibT_eX]

[DOI]

Cleo Sgouropoulou

Ioannis Voyiatzis

Anastasios Koutoumanos

Giuseppe Airo Farulla

Peeter Ellervee

Carlos Delgado Kloos

Raquel M. Crespo García

Proceedings of the 2017 IEEE Global Engineering Education Conference, 2017

Interconnect networks for resistive computing architectures.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Memristive devices: Technology, design automation and computing frontiers.

[BibT_eX]

[DOI]

Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

Region based containers - A new paradigm for the analysis of fault tolerant networks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

On the robustness of memristor based logic gates.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2017

Mitigation of sense amplifier degradation using input switching.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Memristor for computing: Myth or reality?

[BibT_eX]

[DOI]

Hesham Mostafa Elsayed

Henk Corporaal

Koen Bertels

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Test and Reliability of Emerging Non-volatile Memories.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Asian Test Symposium, 2017

2016

Alternative Architectures Toward Reliable Memristive Crossbar Memories.

[BibT_eX]

[DOI]

Ioannis Vourkas

Dimitrios Stathis

Georgios Ch. Sirakoulis

IEEE Trans. Very Large Scale Integr. Syst., 2016

SIERRA - Simulation environment for memory redundancy algorithms.

[BibT_eX]

[DOI]

Simul. Model. Pract. Theory, 2016

Editorial Note on Memristor Models, Circuits and Architectures.

[BibT_eX]

[DOI]

Georgios Ch. Sirakoulis

Int. J. Unconv. Comput., 2016

RRAM variability and its mitigation schemes.

[BibT_eX]

[DOI]

Proceedings of the 26th International Workshop on Power and Timing Modeling, 2016

Skeleton-based design and simulation flow for Computation-in-Memory architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Synthesizing HDL to memristor technology: A generic framework.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Quantification of Sense Amplifier Offset Voltage Degradation due to Zero-and Run-Time Variability.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Instruction cache aging mitigation through Instruction Set Encoding.

[BibT_eX]

[DOI]

Fabian Oboril

Haralampos-G. D. Stratigopoulos

Proceedings of the 17th International Symposium on Quality Electronic Design, 2016

Parallel matrix multiplication on memristor-based computation-in-memory architecture.

[BibT_eX]

[DOI]

Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Non-volatile look-up table based FPGA implementations.

[BibT_eX]

[DOI]

Proceedings of the 11th International Design & Test Symposium, 2016

ETS 2016 foreword.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

Read path degradation analysis in SRAM.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

Boolean logic gate exploration for memristor crossbar.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

Comparative BTI analysis for various sense amplifier designs.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

2015

Yield Improvement for 3D Wafer-to-Wafer Stacked ICs Using Wafer Matching.

[BibT_eX]

[DOI]

Erik Jan Marinissen

ACM Trans. Design Autom. Electr. Syst., 2015

Post-Bond Interconnect Test and Diagnosis for 3-D Memory Stacked on Logic.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Intelligent Voltage Ramp-Up Time Adaptation for Temperature Noise Reduction on Memory-Based PUF Systems.

[BibT_eX]

[DOI]

Mafalda Cortez

Ali Kaichouhi

Vincent van der Leest

Roel Maes

Geert Jan Schrijen

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Testing Open Defects in Memristor-Based Memories.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

A DfT Architecture and Tool Flow for 3-D SICs With Test Data Compression, Embedded Cores, and Multiple Towers.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Dependable Multicore Architectures at Nanoscale: The View From Europe.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

Computation in Memory for Data-Intensive Applications: Beyond CMOS and beyond Von- Neumann.

[BibT_eX]

[DOI]

Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015

Interconnect networks for memristor crossbar.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Computation-in-memory based parallel adder.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

Design dependent SRAM PUF robustness analysis.

[BibT_eX]

[DOI]

Mafalda Cortez

Ryoichi Ishihara

Proceedings of the 16th Latin-American Test Symposium, 2015

SW-based transparent in-field memory testing.

[BibT_eX]

[DOI]

Paolo Bernardi

Lyl M. Ciganda Brasca

Matteo Sonza Reorda

Proceedings of the 16th Latin-American Test Symposium, 2015

Keynote 2: "Computing for big-data: Beyond CMOS and beyond Von-Neumann".

[BibT_eX]

[DOI]

Proceedings of the 10th International Design & Test Symposium, 2015

BTI analysis of SRAM write driver.

[BibT_eX]

[DOI]

Proceedings of the 10th International Design & Test Symposium, 2015

Fast boolean logic mapped on memristor crossbar.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

On resistive open defect detection in DRAMs: The charge accumulation effect.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Electronics and computing in nano-era: The good, the bad and the challenging.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Comparative analysis of RD and Atomistic trap-based BTI models on SRAM Sense Amplifier.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

Memristor based computation-in-memory architecture for data-intensive applications.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Aging mitigation in memory arrays using self-controlled bit-flipping technique.

[BibT_eX]

[DOI]

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Layout-Based Refined NPSF Model for DRAM Characterization and Testing.

[BibT_eX]

[DOI]

Yiorgos Sfikas

Yiorgos Tsiatouhas

IEEE Trans. Very Large Scale Integr. Syst., 2014

Testing Methods for PUF-Based Secure Key Storage Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Quality versus cost analysis for 3D Stacked ICs.

[BibT_eX]

[DOI]

Erik Jan Marinissen

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Direct probing on large-array fine-pitch micro-bumps of a wide-I/O logic-memory interface.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Test Conference, 2014

Line graph based fast rerouting and reconfiguration for handling transient and permanent node failures.

[BibT_eX]

[DOI]

Prashant D. Joshi

Proceedings of the IEEE 15th International Conference on High Performance Switching and Routing, 2014

Memristor based memories: Technology, design and test.

[BibT_eX]

[DOI]

Hassan Aziza

Georgios Ch. Sirakoulis

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

3D/ 2.5D stacked IC cost modeling and test flow selection.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Shortest path reduction in a class of uniform fault tolerant networks.

[BibT_eX]

[DOI]

Prashant D. Joshi

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Security methods in fault tolerant modified line graph based networks.

[BibT_eX]

[DOI]

Prashant D. Joshi

Proceedings of the 2014 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2014

Interconnect test for 3D stacked memory-on-logic.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Bias Temperature Instability analysis of FinFET based SRAM cells.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Hacking and protecting IC hardware.

[BibT_eX]

[DOI]

Jean-Luc Danger

Giorgio Di Natale

Fethulah Smailbegovic

Gerard van Battum

Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Testing PUF-based secure key storage circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Region Disjoint Paths in a Class of Optimal Line Graph Networks.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Computational Science and Engineering, 2014

2013

Guest Editorial - Special Issue on Manufacturable and Dependable Multicore Architectures at Nanoscale (MEDIAN).

[BibT_eX]

[DOI]

Dimitris Gizopoulos

Hans A. R. Manhaeve

J. Electron. Test., 2013

Exploring test opportunities for memory and interconnects in 3D ICs.

[BibT_eX]

[DOI]

Mihai Lefter

Proceedings of the 8th International Design and Test Symposium, 2013

Reducing random-dopant fluctuation impact on core-speed and power variability in many-core platforms.

[BibT_eX]

[DOI]

Sohaib Majzoub

Proceedings of the 8th International Design and Test Symposium, 2013

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

BTI impact on SRAM sense amplifier.

[BibT_eX]

[DOI]

Innocent Agbo

Proceedings of the 8th International Design and Test Symposium, 2013

Adapting voltage ramp-up time for temperature noise reduction on memory-based PUFs.

[BibT_eX]

[DOI]

Mafalda Cortez

Vincent van der Leest

Roel Maes

Geert Jan Schrijen

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Automated DfT insertion and test generation for 3D-SICs with embedded cores and multiple towers.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Bias temperature instability analysis in SRAM decoder.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE European Test Symposium, 2013

Panel session what is the electronics industry doing to win the battle against the expected scary failure rates in future technology nodes?

[BibT_eX]

[DOI]

Srikanth Venkataraman

Proceedings of the 18th IEEE European Test Symposium, 2013

Impact of mid-bond testing in 3D stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Is TSV-based 3D integration suitable for inter-die memory repair?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Reliability challenges of real-time systems in forthcoming technology nodes.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

An Efficient Method for the Test of Embedded Memory Cores during the Operational Phase.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asian Test Symposium, 2013

Using 3D-COSTAR for 2.5D test cost optimization.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International 3D Systems Integration Conference (3DIC), 2013

2012

Test Impact on the Overall Die-to-Wafer 3D Stacked IC Cost.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.

[BibT_eX]

[DOI]

J. Electron. Test., 2012

Testing Embedded Memories: A Survey.

[BibT_eX]

[DOI]

Proceedings of the Mathematical and Engineering Methods in Computer Science, 2012

VLSI Test technology: Why is the field not sexy enough?

[BibT_eX]

[DOI]

Rob Aitken

Proceedings of the 17th IEEE European Test Symposium, 2012

ALU based address generation for RAMs.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

On optimizing test cost for Wafer-to-Wafer 3D-stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 7th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2012

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

Modeling SRAM start-up behavior for Physical Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

BTI impact on logical gates in nano-scale CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

TSV based 3D stacked ICs: Opportunities and challenges.

[BibT_eX]

[DOI]

Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

DfT schemes for resistive open defects in RRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011

Redundant Residue Number System Code for Fault-Tolerant Hybrid Memories.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2011

Generic, orthogonal and low-cost March Element based memory BIST.

[BibT_eX]

[DOI]

Halil Kukner

Proceedings of the 2011 IEEE International Test Conference, 2011

Modeling and mitigating NBTI in nanoscale circuits.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International On-Line Testing Symposium (IOLTS 2011), 2011

On modeling and optimizing cost in 3D Stacked-ICs.

[BibT_eX]

[DOI]

Erik Jan Marinissen

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

ReverseAge: An online NBTI combating technique using time borrowing.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International Design and Test Workshop, 2011

Layer Redundancy Based Yield Improvement for 3D Wafer-to-Wafer Stacked Memories.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

Memory Test Optimization for Parasitic Bit Line Coupling in SRAMs.

[BibT_eX]

[DOI]

Sandra Irobi

Proceedings of the 16th European Test Symposium, 2011

A Schematic-Based Extraction Methodology for Dislocation Defects in Analog/Mixed-Signal Devices.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

NBTI Monitoring and Design for Reliability in Nanoscale Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Reducing Test Power for Embedded Memories.

[BibT_eX]

[DOI]

Ahmed Awad

Abdallatif S. Abu-Issa

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Stacking order impact on overall 3D die-to-wafer Stacked-IC cost.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Influence of parasitic memory effect on single-cell faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

Cost-efficient fault-tolerant decoder for hybrid nanoelectronic memories.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Testing for Parasitic Memory Effect in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

On Defect Oriented Testing for Hybrid CMOS/Memristor Memory.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

Yield Improvement and Test Cost Optimization for 3D Stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE Asian Test Symposium, 2011

A New Test Paradigm for Semiconductor Memories in the Nano-Era.

[BibT_eX]

[DOI]

Venkataraman Krishnaswami

Ijeoma Sandra Irobi

Proceedings of the 20th IEEE Asian Test Symposium, 2011

2010

Bit line coupling memory tests for single-cell fails in SRAMs.

[BibT_eX]

[DOI]

Sandra Irobi

Proceedings of the 28th IEEE VLSI Test Symposium, 2010

On maximizing the compound yield for 3D Wafer-to-Wafer stacked ICs.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Test Conference, 2010

Detecting memory faults in the presence of bit line coupling in SRAM devices.

[BibT_eX]

[DOI]

Sandra Irobi

Proceedings of the 2011 IEEE International Test Conference, 2010

Temperature dependence of NBTI induced delay.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International On-Line Testing Symposium (IOLTS 2010), 2010

ECC design for fault-tolerant crossbar memories: A case study.

[BibT_eX]

[DOI]

Zaiyan Ahyadi

Proceedings of the 5th International Design and Test Workshop, 2010

MBIST architecture framework based on orthogonal constructs.

[BibT_eX]

[DOI]

Proceedings of the 5th International Design and Test Workshop, 2010

High-Performance Cluster-Fault Tolerance Scheme for Hybrid Nanoelectronic Memories.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010

Advanced embedded memory testing: Reducing the defect per million level at lower test cost.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Low-cost, customized and flexible SRAM MBIST engine.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

Using a CISC microcontroller to test embedded memories.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

NBTI modeling in the framework of temperature variation.

[BibT_eX]

[DOI]

Seyab

Proceedings of the Design, Automation and Test in Europe, 2010

Memory testing with a RISC microcontroller.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Test Cost Analysis for 3D Die-to-Wafer Stacking.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE Asian Test Symposium, 2010

2009

Instruction-Level Fault Tolerance Configurability.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2009

Emerging non-CMOS nanoelectronic devices - What are they?.

[BibT_eX]

[DOI]

Sorin Cotofana

Proceedings of the 4th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2009

Residue-based code for reliable hybrid memories.

[BibT_eX]

[DOI]

Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Using RRNS Codes for Cluster Faults Tolerance in Hybrid Memories.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

Testing Embedded Memories in the Nano-Era: Will the Existing Approaches Survive?.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

New Algorithms for Address Decoder Delay Faults and Bit Line Imbalance Faults.

[BibT_eX]

[DOI]

Georgi Nedeltchev Gaydadjiev

Proceedings of the Eighteentgh Asian Test Symposium, 2009

Fault Diagnosis Using Test Primitives in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the Eighteentgh Asian Test Symposium, 2009

2008

Test Set Development for Cache Memory in Modern Microprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

Defect Oriented Testing of the Strap Problem Under Process Variations in DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Test Conference, 2008

2007

Optimizing Test Length for Soft Faults in DRAM Devices.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE VLSI Test Symposium (VTS 2007), 2007

PPM Reduction on Embedded Memories in System on Chip.

[BibT_eX]

[DOI]

Proceedings of the 12th European Test Symposium, 2007

Manifestation of Precharge Faults in High Speed DRAM Devices.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Opens and Delay Faults in CMOS RAM Address Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

DRAM-Specific Space of Memory Tests.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Test Conference, 2006

Space of DRAM fault models and corresponding testing.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

2005

New data-background sequences and their industrial evaluation for word-oriented random-access memories.

[BibT_eX]

[DOI]

John Eleazar Q. Delos Reyes

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Impact of stresses on the fault coverage of memory tests.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Workshop on Memory Technology, 2005

Framework for Fault Analysis and Test Generation in DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Investigations of Faulty DRAM Behavior Using Electrical Simulation Versus an Analytical Approach.

[BibT_eX]

[DOI]

Jörg E. Vollrath

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

Linked faults in random access memories: concept, fault models, test algorithms, and industrial results.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Memory Fault Modeling Trends: A Case Study.

[BibT_eX]

[DOI]

J. Electron. Test., 2004

Effects of Bit Line Coupling on the Faulty Behavior of DRAMs.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE VLSI Test Symposium (VTS 2004), 2004

The State-of-Art and Future Trends in Testing Embedded Memories.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

The Effectiveness of the Scan Test and Its New Variants.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International Workshop on Memory Technology, 2004

Detecting Faults in the Peripheral Circuits and an Evaluation of SRAM Tests.

[BibT_eX]

[DOI]

Rob Wadsworth

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Tests for address decoder delay faults in RAMs due to inter-gate opens.

[BibT_eX]

[DOI]

Proceedings of the 9th European Test Symposium, 2004

Evaluation of Intra-Word Faults in Word-Oriented RAMs.

[BibT_eX]

[DOI]

John Delos Reyes

Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004

2003

Dynamic Faults in Random-Access-Memories: Concept, Fault Models and Tests.

[BibT_eX]

[DOI]

J. Electron. Test., 2003

Detecting Intra-Word Faults in Word-Oriented Memories.

[BibT_eX]

[DOI]

Mike Rodgers

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

A Fault Primitive Based Analysis of Linked Faults in RAMs.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International Workshop on Memory Technology, 2003

Importance of dynamic faults for new SRAM technologies.

[BibT_eX]

[DOI]

Proceedings of the 8th European Test Workshop, 2003

March SL: A Test For All Static Linked Memory Faults.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

Thorough testing of any multiport memory with linear tests.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Efficient Tests for Realistic Faults in Dual-Port SRAMs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Testing Static and Dynamic Faults in Random Access Memories.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

March SS: A Test for All Static Simple RAM Faults.

[BibT_eX]

[DOI]

Mike Rodgers

Proceedings of the 10th IEEE International Workshop on Memory Technology, 2002

2001

Realistic Fault Models and Test Procedures for Multi-Port SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International Workshop on Memory Technology, 2001

Detecting Unique Faults in Multi-port SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

Testing Address Decoder Faults in Two-Port Memories: Fault Models, Tests, Consequences of Port Restrictions, and Test Strategy.

[BibT_eX]

[DOI]

J. Electron. Test., 2000

March Tests for Realistic Faults in Two-Port Memories.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International Workshop on Memory Technology, 2000

An experimental analysis of spot defects in SRAMs: realistic fault models and tests.

[BibT_eX]

[DOI]

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Port interference faults in two-port memories.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

March Tests for Word-Oriented Two-Port Memories.

[BibT_eX]

[DOI]

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

Fault Models and Tests for Two-Port Memories.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998

Consequences of port restrictions on testing two-port memories.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Consequences of Port Restriction on Testing Address Decoders in Two-Port Memories.

[BibT_eX]

[DOI]